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Date: Mon, 18 Mar 2024 08:42:39 +0800 Message-Id: <20240318004239.237755-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org It fixes ICE of unrecognized logic operation insn which is generated by lroundmn2 expanders. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. gcc/ChangeLog: PR target/114334 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF. (MODEF248): New mode iterator. (ssevecmodesuffix): Hanlde BF and HF. * config/i386/sse.md (andnot3): Extend to HF/BF. (3): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr114334.c: New test. --- gcc/config/i386/i386.md | 13 +++++++++---- gcc/config/i386/sse.md | 22 +++++++++++----------- gcc/testsuite/gcc.target/i386/pr114334.c | 8 ++++++++ 3 files changed, 28 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr114334.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index df97a2d6270..11fdc6af3fa 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -543,8 +543,9 @@ (define_attr "type" ;; Main data type used by the insn (define_attr "mode" - "unknown,none,QI,HI,SI,DI,TI,OI,XI,HF,BF,SF,DF,XF,TF,V32HF,V16HF,V8HF, - V16SF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,V8DF,V4HF,V4BF,V2HF,V2BF" + "unknown,none,QI,HI,SI,DI,TI,OI,XI,HF,BF,SF,DF,XF,TF, + V32HF,V16HF,V8HF,V4HF,V2HF,V32BF,V16BF,V8BF,V4BF,V2BF, + V16SF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,V8DF" (const_string "unknown")) ;; The CPU unit operations uses. @@ -1323,6 +1324,8 @@ (define_mode_attr ashl_input_operand ;; SSE and x87 SFmode and DFmode floating point modes (define_mode_iterator MODEF [SF DF]) +(define_mode_iterator MODEF248 [BF HF SF (DF "TARGET_SSE2")]) + ;; SSE floating point modes (define_mode_iterator MODEFH [(HF "TARGET_AVX512FP16") SF DF]) @@ -1347,7 +1350,8 @@ (define_mode_attr ssemodesuffix (V64QI "b") (V32HI "w") (V16SI "d") (V8DI "q")]) ;; SSE vector suffix for floating point modes -(define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")]) +;; BF HF use same suffix as SF for logic operations. +(define_mode_attr ssevecmodesuffix [(BF "ps") (HF "ps") (SF "ps") (DF "pd")]) ;; SSE vector mode corresponding to a scalar mode (define_mode_attr ssevecmode @@ -1357,7 +1361,8 @@ (define_mode_attr ssevecmodelower ;; AVX512F vector mode corresponding to a scalar mode (define_mode_attr avx512fvecmode - [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")]) + [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") + (HF "V32HF") (BF "V32BF") (SF "V16SF") (DF "V8DF")]) ;; Instruction suffix for REX 64bit operators. (define_mode_attr rex64suffix [(SI "{l}") (DI "{q}")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1bc614ab702..3286d3a4fac 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5125,12 +5125,12 @@ (define_expand "signbit2" ;; because the native instructions read the full 128-bits. (define_insn "*andnot3" - [(set (match_operand:MODEF 0 "register_operand" "=x,x,v,v") - (and:MODEF - (not:MODEF - (match_operand:MODEF 1 "register_operand" "0,x,v,v")) - (match_operand:MODEF 2 "register_operand" "x,x,v,v")))] - "SSE_FLOAT_MODE_P (mode)" + [(set (match_operand:MODEF248 0 "register_operand" "=x,x,v,v") + (and:MODEF248 + (not:MODEF248 + (match_operand:MODEF248 1 "register_operand" "0,x,v,v")) + (match_operand:MODEF248 2 "register_operand" "x,x,v,v")))] + "TARGET_SSE" { char buf[128]; const char *ops; @@ -5257,11 +5257,11 @@ (define_insn "*andnot3" (const_string "TI")))]) (define_insn "3" - [(set (match_operand:MODEF 0 "register_operand" "=x,x,v,v") - (any_logic:MODEF - (match_operand:MODEF 1 "register_operand" "%0,x,v,v") - (match_operand:MODEF 2 "register_operand" "x,x,v,v")))] - "SSE_FLOAT_MODE_P (mode)" + [(set (match_operand:MODEF248 0 "register_operand" "=x,x,v,v") + (any_logic:MODEF248 + (match_operand:MODEF248 1 "register_operand" "%0,x,v,v") + (match_operand:MODEF248 2 "register_operand" "x,x,v,v")))] + "TARGET_SSE" { char buf[128]; const char *ops; diff --git a/gcc/testsuite/gcc.target/i386/pr114334.c b/gcc/testsuite/gcc.target/i386/pr114334.c new file mode 100644 index 00000000000..8e38e24cd16 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr114334.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -mavx512fp16" } */ + +long +foo(_Float16 f) +{ + return __builtin_lroundf16(f); +}