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X-IronPort-AV: E=McAfee;i="6600,9927,11010"; a="5094678" X-IronPort-AV: E=Sophos;i="6.07,118,1708416000"; d="scan'208";a="5094678" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 00:06:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,118,1708416000"; d="scan'208";a="16127984" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa005.jf.intel.com with ESMTP; 12 Mar 2024 00:06:47 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1D50A1006FE6; Tue, 12 Mar 2024 15:06:47 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, yanzhang.wang@intel.com, Pan Li Subject: [PATCH v1] RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC] Date: Tue, 12 Mar 2024 15:06:35 +0800 Message-Id: <20240312070635.4124681-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li Notice some code style issue(s) when add __riscv_v_fixed_vlen, includes: * Meanless empty line. * Line greater than 80 chars. * Indent with 3 space(s). * Argument unalignment. gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix code style greater than 80 chars. (riscv_cpu_cpp_builtins): Fix useless empty line, indent with 3 space(s) and argument unalignment. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-c.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 3755ec0b8ef..7029ba88186 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -37,7 +37,8 @@ along with GCC; see the file COPYING3. If not see static int riscv_ext_version_value (unsigned major, unsigned minor) { - return (major * RISCV_MAJOR_VERSION_BASE) + (minor * RISCV_MINOR_VERSION_BASE); + return (major * RISCV_MAJOR_VERSION_BASE) + + (minor * RISCV_MINOR_VERSION_BASE); } /* Implement TARGET_CPU_CPP_BUILTINS. */ @@ -110,7 +111,6 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) case CM_MEDANY: builtin_define ("__riscv_cmodel_medany"); break; - } if (riscv_user_wants_strict_align) @@ -142,9 +142,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) riscv_ext_version_value (0, 12)); } - if (TARGET_XTHEADVECTOR) - builtin_define_with_int_value ("__riscv_th_v_intrinsic", - riscv_ext_version_value (0, 11)); + if (TARGET_XTHEADVECTOR) + builtin_define_with_int_value ("__riscv_th_v_intrinsic", + riscv_ext_version_value (0, 11)); /* Define architecture extension test macros. */ builtin_define_with_int_value ("__riscv_arch_test", 1);