From patchwork Tue Feb 27 13:56:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1905109 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TkfFG4B7lz23qQ for ; Wed, 28 Feb 2024 00:57:38 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7E59A3858C35 for ; Tue, 27 Feb 2024 13:57:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 6CEFC385841E for ; Tue, 27 Feb 2024 13:57:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6CEFC385841E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6CEFC385841E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709042231; cv=none; b=dtkvX59xtLQkJo09OqclK60Sl1nMtU0f5hYtVw8DlpYbcCIBvOEcRcgTlZwvzCFt6LkjO+AynvXHeLwBfhwf8tNq7XF+lke/95/u+LO4JlPwTaqaossL8DhFgFzb5apAUu3uwAJmJsoplJmDEsSu9vnN1qGgEBtA30zl7Qr42g0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709042231; c=relaxed/simple; bh=uDG2UZeAYbceNVn4GsVeeNuW49KNhGSXLTw8e8Zi80Y=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=rpfkY3OE8OE24LL/yUAIn+fdTTe4aLQyNbhT5y6U71zAhKFEB/OqVXl0oM6tqg2HeDFLNCd1TYufDwkjS0ocmhAD+4N679JLc/CXBmoBs9tXI06VWj/kB3AJQ3DD3c1a68rCjjx9psusPcT4SIUAWM/n1E4+bzf+DietopyNNbU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 64BD3FEC; Tue, 27 Feb 2024 05:57:47 -0800 (PST) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 55F203F762; Tue, 27 Feb 2024 05:57:08 -0800 (PST) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: stam.markianos-wright@arm.com, richard.earnshaw@arm.com, Andre Vieira Subject: [PATCH v6 2/5] arm: Annotate instructions with mve_safe_imp_xlane_pred Date: Tue, 27 Feb 2024 13:56:44 +0000 Message-Id: <20240227135647.30404-3-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240227135647.30404-1-andre.simoesdiasvieira@arm.com> References: <20240227135647.30404-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch annotates some MVE across lane instructions with a new attribute. We use this attribute to let the compiler know that these instructions can be safely implicitly predicated when tail predicating if their operands are guaranteed to have zeroed tail predicated lanes. These instructions were selected because having the value 0 in those lanes or 'tail-predicating' those lanes have the same effect. gcc/ChangeLog: * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute. * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator attribute. * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u, vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u, vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u, vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s, vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s, vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u, vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u, vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s, vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s, vmlsldavaxq_s): Added mve_safe_imp_xlane_pred. --- gcc/config/arm/arm.md | 6 ++++++ gcc/config/arm/iterators.md | 8 ++++++++ gcc/config/arm/mve.md | 12 ++++++++++++ 3 files changed, 26 insertions(+) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 81290e83818..814e871acea 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -130,6 +130,12 @@ (define_attr "predicated" "yes,no" (const_string "no")) ; encode that it is a predicable instruction. (define_attr "mve_unpredicated_insn" "" (symbol_ref "CODE_FOR_nothing")) +; An attribute used by the loop-doloop pass when determining whether it is +; safe to predicate a MVE instruction, that operates across lanes, and was +; previously not predicated. The pass will still check whether all inputs +; are predicated by the VCTP predication mask. +(define_attr "mve_safe_imp_xlane_pred" "yes,no" (const_string "no")) + ; LENGTH of an instruction (in bytes) (define_attr "length" "" (const_int 4)) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 7600bf62531..22b3ddf5637 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -869,6 +869,14 @@ (define_code_attr mve_addsubmul [ (plus "vadd") ]) +(define_int_attr mve_vmaxmin_safe_imp [ + (VMAXVQ_U "yes") + (VMAXVQ_S "no") + (VMAXAVQ_S "yes") + (VMINVQ_U "no") + (VMINVQ_S "no") + (VMINAVQ_S "no")]) + (define_int_attr mve_cmp_op1 [ (VCMPCSQ_M_U "cs") (VCMPEQQ_M_S "eq") (VCMPEQQ_M_U "eq") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 8aa0bded7f0..d7bdcd862f8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -393,6 +393,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%0, %q1" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -529,6 +530,7 @@ (define_insn "@mve_q_v4si" "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q1" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -802,6 +804,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%0, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1014,6 +1017,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%0, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "") (set_attr "type" "mve_move") ]) @@ -1033,6 +1037,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%0, %q1, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1219,6 +1224,7 @@ (define_insn "@mve_q_v4si" "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1450,6 +1456,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%Q0, %R0, %q1, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1588,6 +1595,7 @@ (define_insn "@mve_q_v4si" "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q1, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1725,6 +1733,7 @@ (define_insn "@mve_q_v4si" "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1742,6 +1751,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1952,6 +1962,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -2401,6 +2412,7 @@ (define_insn "@mve_q_" "TARGET_HAVE_MVE" ".%#\t%Q0, %R0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ])