diff mbox series

RISC-V: Tweak the wording for the sorry message

Message ID 20240119023457.1870618-1-kito.cheng@sifive.com
State New
Headers show
Series RISC-V: Tweak the wording for the sorry message | expand

Commit Message

Kito Cheng Jan. 19, 2024, 2:34 a.m. UTC 
Use "does not" rather than "cannot", because it's implementation issue.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
	sorry message.
---
 gcc/config/riscv/riscv.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

钟居哲 Jan. 19, 2024, 2:35 a.m. UTC | #1 
OK



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2024-01-19 10:34
To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
CC: Kito Cheng
Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
Use "does not" rather than "cannot", because it's implementation issue.
 
gcc/ChangeLog:
 
* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
sorry message.
---
gcc/config/riscv/riscv.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129397f..dd6e68a08c2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
      We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
   if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
-    sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+    sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
   "'V' Extension");
   /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
      big-endian after finishing full coverage testing.  */
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
-    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+    sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits (opts);
Kito Cheng Jan. 19, 2024, 2:41 a.m. UTC | #2 
Thanks, pushed to trunk :)

On Fri, Jan 19, 2024 at 10:36 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> OK
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-01-19 10:34
> To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
> CC: Kito Cheng
> Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
> Use "does not" rather than "cannot", because it's implementation issue.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
> sorry message.
> ---
> gcc/config/riscv/riscv.cc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index f1d5129397f..dd6e68a08c2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
>       We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
>    if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
> -    sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
> +    sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
>    "'V' Extension");
>    /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
>       big-endian after finishing full coverage testing.  */
>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
> -    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
> +    sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>    /* Convert -march to a chunks count.  */
>    riscv_vector_chunks = riscv_convert_vector_bits (opts);
> --
> 2.34.1
>
>
Bernhard Reutner-Fischer Jan. 19, 2024, 9:40 a.m. UTC | #3 
On 19 January 2024 03:41:57 CET, Kito Cheng <kito.cheng@gmail.com> wrote:
>Thanks, pushed to trunk :)

Thanks, but don't you have to update the tests too, at least
gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c ?

thanks

>
>On Fri, Jan 19, 2024 at 10:36 AM juzhe.zhong@rivai.ai
><juzhe.zhong@rivai.ai> wrote:
>>
>> OK
>>
>> ________________________________
>> juzhe.zhong@rivai.ai
>>
>>
>> From: Kito Cheng
>> Date: 2024-01-19 10:34
>> To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
>> CC: Kito Cheng
>> Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
>> Use "does not" rather than "cannot", because it's implementation issue.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
>> sorry message.
>> ---
>> gcc/config/riscv/riscv.cc | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index f1d5129397f..dd6e68a08c2 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
>>       We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
>>    if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
>> -    sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
>> +    sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
>>    "'V' Extension");
>>    /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
>>       big-endian after finishing full coverage testing.  */
>>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
>> -    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
>> +    sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>>    /* Convert -march to a chunks count.  */
>>    riscv_vector_chunks = riscv_convert_vector_bits (opts);
>> --
>> 2.34.1
>>
>>
钟居哲 Jan. 19, 2024, 9:43 a.m. UTC | #4 
Yeah. There is regression here:

Executing on host: /work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/xgcc -B/work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/  /work/home/jzzhong/work/docker/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c  -march=rv64gcv -mabi=lp64d -mcmodel=medany   -fdiagnostics-plain-output   -march=rv64gcv -mabi=lp64d -mbig-endian -O3 -S   -o big_endian-1.s    (timeout = 600000)
spawn -ignore SIGHUP /work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/xgcc -B/work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/ /work/home/jzzhong/work/docker/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c -march=rv64gcv -mabi=lp64d -mcmodel=medany -fdiagnostics-plain-output -march=rv64gcv -mabi=lp64d -mbig-endian -O3 -S -o big_endian-1.s^M
cc1: sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode^M
compiler exited with status 1
XFAIL: gcc.target/riscv/rvv/base/big_endian-1.c (test for excess errors)
Excess errors:
cc1: sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode

Executing on host: /work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/xgcc -B/work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/  /work/home/jzzhong/work/docker/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c  -march=rv64gcv -mabi=lp64d -mcmodel=medany   -fdiagnostics-plain-output   -march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3 -S   -o big_endian-2.s    (timeout = 600000)
spawn -ignore SIGHUP /work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/xgcc -B/work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/ /work/home/jzzhong/work/docker/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c -march=rv64gcv -mabi=lp64d -mcmodel=medany -fdiagnostics-plain-output -march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3 -S -o big_endian-2.s^M
cc1: sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode^M
compiler exited with status 1
XFAIL: gcc.target/riscv/rvv/base/big_endian-2.c (test for excess errors)
Excess errors:
cc1: sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode

I think zvl_unimplemented-1.c and zvl_unimplemented-2.c should also be fixed.



juzhe.zhong@rivai.ai
 
From: rep.dot.nop
Date: 2024-01-19 17:40
To: Kito Cheng; juzhe.zhong@rivai.ai
CC: Kito.cheng; jeffreyalaw; Robin Dapp; gcc-patches
Subject: Re: [PATCH] RISC-V: Tweak the wording for the sorry message
On 19 January 2024 03:41:57 CET, Kito Cheng <kito.cheng@gmail.com> wrote:
>Thanks, pushed to trunk :)
 
Thanks, but don't you have to update the tests too, at least
gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c ?
 
thanks
 
>
>On Fri, Jan 19, 2024 at 10:36 AM juzhe.zhong@rivai.ai
><juzhe.zhong@rivai.ai> wrote:
>>
>> OK
>>
>> ________________________________
>> juzhe.zhong@rivai.ai
>>
>>
>> From: Kito Cheng
>> Date: 2024-01-19 10:34
>> To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
>> CC: Kito Cheng
>> Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
>> Use "does not" rather than "cannot", because it's implementation issue.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
>> sorry message.
>> ---
>> gcc/config/riscv/riscv.cc | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index f1d5129397f..dd6e68a08c2 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
>>       We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
>>    if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
>> -    sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
>> +    sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
>>    "'V' Extension");
>>    /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
>>       big-endian after finishing full coverage testing.  */
>>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
>> -    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
>> +    sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>>    /* Convert -march to a chunks count.  */
>>    riscv_vector_chunks = riscv_convert_vector_bits (opts);
>> --
>> 2.34.1
>>
>>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129397f..dd6e68a08c2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@  riscv_override_options_internal (struct gcc_options *opts)
 
      We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
   if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
-    sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+    sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
 	   "'V' Extension");
 
   /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
      big-endian after finishing full coverage testing.  */
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
-    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+    sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits (opts);