From patchwork Thu Jan 11 11:23:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 1885530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T9j3S0Bbyz1yPp for ; Thu, 11 Jan 2024 22:23:48 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 04929386182A for ; Thu, 11 Jan 2024 11:23:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id 981763860760 for ; Thu, 11 Jan 2024 11:23:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 981763860760 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 981763860760 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704972205; cv=none; b=bbqAuQ7iYDo7o2+YKZJifVPpHPK4YWwl80wz3brKKYO9C+4prFxlAmRqjPNDnBjkDwceUSkBxHqmDb551LngALtpkTxJQMvC6cW2PndxpDfJ0MGV3V3tcZYrcK+1s4RjNQTXPntkba0fsxo9ongSNYEj3rjwh2wRWuTFN7q4VUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704972205; c=relaxed/simple; bh=jRTUJp7bkTqJuRuUEOF/QXW2e69N+PTSlHHiiHqJYJk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=S6crO8MnWT7InZ4aq+dQqiGOJDNGVp4kN/TkMGF9EG07dQ7XRlDLi78VYlW80y9/P+Z5i0196GN2DUmOYtOY005yNW5EwKMwHnt/NG8vgQFvqbiaSDmlFSX1qzftqiXSwyczJVLrBIk9+M+1ph8uOXtFBNHOWVeUNItk8r0j3cI= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R141e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045170; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=10; SR=0; TI=SMTPD_---0W-PMTMg_1704972193; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0W-PMTMg_1704972193) by smtp.aliyun-inc.com; Thu, 11 Jan 2024 19:23:15 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@dabbelt.com, richard.sandiford@arm.com, kito.cheng@gmail.com, christoph.muellner@vrull.eu, rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: THEAD: Fix ICE caused by split optimizations for XTheadFMemIdx. Date: Thu, 11 Jan 2024 19:23:04 +0800 Message-Id: <20240111112304.1398-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-19.4 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Due to the premature split optimizations for XTheadFMemIdx, GPR is allocated when reload allocates registers, resulting in the following insn. (insn 66 21 64 5 (set (reg:DF 14 a4 [orig:136 ] [136]) (mem:DF (plus:SI (reg/f:SI 15 a5 [141]) (ashift:SI (reg/v:SI 10 a0 [orig:137 i ] [137]) (const_int 3 [0x3]))) [0 S8 A64])) 218 {*movdf_hardfloat_rv32} (nil)) Since we currently do not support adjustments to th_m_mir/th_m_miu, which will trigger ICE. So it is recommended to place the split optimizations after reload to ensure FPR when registers are allocated. gcc/ChangeLog: * config/riscv/thead.md: Add limits for splits. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmemidx-medany.c: New test. --- gcc/config/riscv/thead.md | 22 ++++++++--- .../gcc.target/riscv/xtheadfmemidx-medany.c | 38 +++++++++++++++++++ 2 files changed, 54 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index e370774d518..5c7d4beb1b6 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -933,14 +933,17 @@ (define_insn_and_split "*th_fmemidx_I_a" && pow2p_hwi (INTVAL (operands[2])) && IN_RANGE (exact_log2 (INTVAL (operands[2])), 1, 3)" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (mem:TH_M_NOEXTF (plus:X (match_dup 3) (ashift:X (match_dup 1) (match_dup 2)))))] { operands[2] = GEN_INT (exact_log2 (INTVAL (operands [2]))); } -) + [(set_attr "move_type" "fpload") + (set_attr "mode" "") + (set_attr "type" "fmove") + (set (attr "length") (const_int 16))]) (define_insn_and_split "*th_fmemidx_I_c" [(set (mem:TH_M_ANYF (plus:X @@ -977,7 +980,7 @@ (define_insn_and_split "*th_fmemidx_US_a" && CONST_INT_P (operands[3]) && (INTVAL (operands[3]) >> exact_log2 (INTVAL (operands[2]))) == 0xffffffff" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (mem:TH_M_NOEXTF (plus:DI (match_dup 4) @@ -985,7 +988,10 @@ (define_insn_and_split "*th_fmemidx_US_a" { operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = GEN_INT (exact_log2 (INTVAL (operands [2]))); } -) + [(set_attr "move_type" "fpload") + (set_attr "mode" "") + (set_attr "type" "fmove") + (set (attr "length") (const_int 16))]) (define_insn_and_split "*th_fmemidx_US_c" [(set (mem:TH_M_ANYF (plus:DI @@ -1020,12 +1026,16 @@ (define_insn_and_split "*th_fmemidx_UZ_a" "TARGET_64BIT && TARGET_XTHEADMEMIDX && TARGET_XTHEADFMEMIDX && (!HARD_REGISTER_NUM_P (REGNO (operands[0])) || HARDFP_REG_P (REGNO (operands[0])))" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) (mem:TH_M_NOEXTF (plus:DI (match_dup 2) (zero_extend:DI (match_dup 1)))))] -) + "" + [(set_attr "move_type" "fpload") + (set_attr "mode" "") + (set_attr "type" "fmove") + (set (attr "length") (const_int 16))]) (define_insn_and_split "*th_fmemidx_UZ_c" [(set (mem:TH_M_ANYF (plus:DI diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c new file mode 100644 index 00000000000..0c8060d0632 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Og" "-Os" "-Oz"} } */ +/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx -mabi=ilp32d -mcmodel=medany -O2" } */ + +typedef union { + double v; + unsigned w; +} my_t; + +double z; + +double foo (int i, int j) +{ + + if (j) + { + switch (i) + { + case 0: + return 1; + case 1: + return 0; + case 2: + return 3.0; + } + } + + if (i == 1) + { + my_t u; + u.v = z; + u.w = 1; + z = u.v; + } + return z; +} + +/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */