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X-IronPort-AV: E=McAfee;i="6600,9927,10947"; a="395268438" X-IronPort-AV: E=Sophos;i="6.04,182,1695711600"; d="scan'208";a="395268438" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2024 23:09:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10947"; a="731378872" X-IronPort-AV: E=Sophos;i="6.04,182,1695711600"; d="scan'208";a="731378872" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 08 Jan 2024 23:09:03 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 4904210079C1; Tue, 9 Jan 2024 15:09:02 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com Subject: [PATCH] i386: [APX] Document inline asm behavior and new switch for APX Date: Tue, 9 Jan 2024 15:07:02 +0800 Message-Id: <20240109070702.413866-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, For APX, the inline asm behavior was not mentioned in any document before. Add description for it. Ok for trunk? gcc/ChangeLog: * config/i386/i386.opt: Adjust document. * doc/invoke.texi: Add description for -mapx-inline-asm-use-gpr32. --- gcc/config/i386/i386.opt | 3 +-- gcc/doc/invoke.texi | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index a38e92baf92..5b4f1bff25f 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1357,8 +1357,7 @@ Enum(apx_features) String(all) Value(apx_all) Set(1) mapx-inline-asm-use-gpr32 Target Var(ix86_apx_inline_asm_use_gpr32) Init(0) -Enable GPR32 in inline asm when APX_EGPR enabled, do not -hook reg or mem constraint in inline asm to GPR16. +Enable GPR32 in inline asm when APX_F enabled. mevex512 Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 68d1f364ac0..47fd96648d8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -35272,6 +35272,13 @@ r8-r15 registers so that the call and jmp instruction length is 6 bytes to allow them to be replaced with @samp{lfence; call *%r8-r15} or @samp{lfence; jmp *%r8-r15} at run-time. +@opindex mapx-inline-asm-use-gpr32 +@item -mapx-inline-asm-use-gpr32 +When APX_F enabled, EGPR usage was by default disabled to prevent +unexpected EGPR generation in instructions that does not support it. +To invoke EGPR usage in inline asm, use this switch to allow EGPR in +inline asm, while user should ensure the asm actually supports EGPR. + @end table These @samp{-m} switches are supported in addition to the above