Message ID | 20240108061126.792885-1-kito.cheng@sifive.com |
---|---|
State | New |
Headers | show |
Series | [committed] RISC-V: Fix testsuite | expand |
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.h index 604e9048055..dfe48d6dae1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.h @@ -105,7 +105,9 @@ int cond[N] = {0}; if (b_##TYPE[i] != a_##TYPE[i]) __builtin_abort(); \ } \ else \ - assert (b_##TYPE[i] == 0); \ + { \ + if (b_##TYPE[i] != 0) __builtin_abort(); \ + } \ } #define run_7(TYPE) \ @@ -151,7 +153,9 @@ int cond[N] = {0}; if (b_##TYPE[i] != a_##TYPE[i]) __builtin_abort(); \ } \ else \ - assert (b_##TYPE[i] == 0); \ + { \ + if (b_##TYPE[i] != 0) __builtin_abort(); \ + } \ } #define run_10(TYPE) \