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[Committed] RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS]

Message ID 20240106051038.213211-1-juzhe.zhong@rivai.ai
State New
Headers show
Series [Committed] RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS] | expand

Commit Message

钟居哲 Jan. 6, 2024, 5:10 a.m. UTC 
This patch fixes a bug of VSETVL PASS in this following situation:

    Ignore curr info since prev info available with it:
      prev_info: VALID (insn 8, bb 2)
        Demand fields: demand_ratio_and_ge_sew demand_avl
        SEW=16, VLMUL=mf4, RATIO=64, MAX_SEW=64
        TAIL_POLICY=agnostic, MASK_POLICY=agnostic
        AVL=(const_int 1 [0x1])
        VL=(nil)
      curr_info: VALID (insn 12, bb 2)
        Demand fields: demand_ge_sew demand_non_zero_avl
        SEW=16, VLMUL=m1, RATIO=16, MAX_SEW=32
        TAIL_POLICY=agnostic, MASK_POLICY=agnostic
        AVL=(const_int 1 [0x1])
        VL=(nil)

We should update prev_info MAX_SEW from 64 into 32.

Before this patch:
foo:
        vsetivli        zero,1,e64,m1,ta,ma
        vle64.v v1,0(a1)
        vmv.s.x v3,a0
        vfmv.s.f        v2,fa0
        vadd.vv v1,v1,v1
        ret

After this patch:
foo:
	vsetivli	zero,1,e16,mf4,ta,ma
	vle64.v	v1,0(a1)
	vmv.s.x	v3,a0
	vfmv.s.f	v2,fa0
	vsetvli	zero,zero,e64,m1,ta,ma
	vadd.vv	v1,v1,v1
	ret

Tested on both RV32 and RV64 no regression. Committed.

	PR target/113248

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr113248.c: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc                | 17 +++++++++++++++++
 .../gcc.target/riscv/rvv/vsetvl/pr113248.c      | 15 +++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c
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Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 3a2ea9ad44a..7d748edc0ef 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2876,6 +2876,23 @@  pre_vsetvl::fuse_local_vsetvl_info ()
 		      curr_info.dump (dump_file, "        ");
 		      fprintf (dump_file, "\n");
 		    }
+		  /* Even though prev_info is available with curr_info,
+		     we need to update the MAX_SEW of prev_info since
+		     we don't check MAX_SEW in available_p check.
+
+		     prev_info:
+		     Demand fields: demand_ratio_and_ge_sew demand_avl
+		     SEW=16, VLMUL=mf4, RATIO=64, MAX_SEW=64
+
+		     curr_info:
+		     Demand fields: demand_ge_sew demand_non_zero_avl
+		     SEW=16, VLMUL=m1, RATIO=16, MAX_SEW=32
+
+		     In the example above, prev_info is available with
+		     curr_info, we need to update prev_info MAX_SEW from
+		     64 into 32.  */
+		  prev_info.set_max_sew (
+		    MIN (prev_info.get_max_sew (), curr_info.get_max_sew ()));
 		  if (!curr_info.vl_used_by_non_rvv_insn_p ()
 		      && vsetvl_insn_p (curr_info.get_insn ()->rtl ()))
 		    m_delete_list.safe_push (curr_info);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c
new file mode 100644
index 00000000000..b3b506177df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mtune=generic-ooo --param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void foo(_Float16 y, int64_t *i64p)
+{
+  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
+  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
+  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
+  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */