From patchwork Sat Jan 6 02:08:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1883167 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T6P0K0X6Zz1yPM for ; Sat, 6 Jan 2024 13:09:36 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E58E8385801D for ; Sat, 6 Jan 2024 02:09:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id DF57E3858C54 for ; Sat, 6 Jan 2024 02:09:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF57E3858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DF57E3858C54 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704506948; cv=none; b=HCWQrd3Ohm5WgXevRQu5fuNY6AeOVcGA9L8WC0cJyF19MWMZusKjA/+f4bzJeEVuhJn3QnWcz7xA44gLtKQj4SEKBTOKh4w5SVH74Mgbuw8mIjKEfsddNGz9QqXwfg7DwfcCJShYrYFGqxNpWGQIZmDe3fAavt5dxNuamWyJpog= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704506948; c=relaxed/simple; bh=Mmko9iZF+ANTX0G10Y1tePiqihqR70FOh1RDIYbSmkM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=uqx+SqQGkI3K8OSJcMGfRhv48ZRG1lIs+dEsBB4/Nfe2P6gStGKFSk+EikRbbSh4zf9rr/uL5DnqX8Tk4k+cJzkS0+naohrbDQauWNq3iqRADPUlDCGEl72jS4eXNX2FaZubPhQHc25y7cEtVSW2O5oxDq76p5SF8U7isxHMWI8= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp77t1704506937tipdhk1y Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 06 Jan 2024 10:08:56 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: ILHsT53NKPi6nYUtz8M3C6+toWPejCjsvBYJNYH+7yd8EFL51EKkpqIqAVbMc 6MCkikpsjkAPuiHA4e17IINPq/vyzeC2/uDdaRYDM0ELUeZ83NL5H4+Szhc+xBWA87vMV1f t7pG/IzFhgYoMvrzc4GmSIiMlAU78GotNCfgNHAfj9/q11CXAHpR//ajk+cl97Lgojx4Hyt iMpPrah+i9pwO5dDxoa5EXHjk2f6iVPUJfKMtKRK5hVWwkHGUyiyRIeIr2PR8oViAh1qssi Rj5qdAQhzi7688hX83FIZxoEpzl4gBHPK5F3Ucj+YSFswgGF6/0yIGR7Agwy4ClEb1ecqok h90EXfFpCC3IBlouxu/HYDlPxqWCfDq15cWqt6B7aMvCrTCNLpgITbaBIhu1q3NmQAisxaK X-QQ-GoodBg: 2 X-BIZMAIL-ID: 872118696786248216 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed V2] RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move Date: Sat, 6 Jan 2024 10:08:55 +0800 Message-Id: <20240106020855.1556409-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org V2: Address comments from Robin. While working on fixing a bug, I notice this following code has redundant move: #include "riscv_vector.h" void f (float x, float y, void *out) { float f[4] = { x, x, x, y }; vfloat32m1_t v = __riscv_vle32_v_f32m1 (f, 4); __riscv_vse32_v_f32m1 (out, v, 4); } Before this patch: f: vsetivli zero,4,e32,m1,ta,ma addi sp,sp,-16 vfmv.v.f v1,fa0 vfslide1down.vf v1,v1,fa1 vmv.v.v v1,v1 ----> redundant move. vse32.v v1,0(a0) addi sp,sp,16 jr ra The rootcause is that the complicate vmv.v.v pattern doesn't simplify it into simple (set (reg) (reg)) reg-to-reg move pattern. Currently, we support such simplification for VLMAX. However, the case I found is non-VLMAX but with LEN = NUNITS which should be considered as equivalent to VLMAX. Add a simple fix for such situation. Tested on both RV32/RV64 no regressions. gcc/ChangeLog: * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function. * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto. * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vf_avl-4.c: New test. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 23 +++++++++++++++++++ gcc/config/riscv/vector.md | 9 ++------ .../gcc.target/riscv/rvv/base/vf_avl-4.c | 13 +++++++++++ 4 files changed, 39 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 0f0337cfb38..00a5b645abe 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -687,6 +687,7 @@ bool imm_avl_p (machine_mode); bool can_be_broadcasted_p (rtx); bool gather_scatter_valid_offset_p (machine_mode); HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); +bool whole_reg_to_reg_move_p (rtx *, machine_mode, int); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index ec859645415..2491522191a 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -5117,4 +5117,27 @@ estimated_poly_value (poly_int64 val, unsigned int kind) return val.coeffs[0] + val.coeffs[1] * over_min_vlen / TARGET_MIN_VLEN; } +/* Return true it is whole register-register move. */ +bool +whole_reg_to_reg_move_p (rtx *ops, machine_mode mode, int avl_type_index) +{ + /* An operation is a whole-register move if either + (1) Its vlmax operand equals VLMAX + (2) Its vl operand equals the number of units of its mode. */ + if (register_operand (ops[0], mode) + && register_operand (ops[3], mode) + && satisfies_constraint_vu (ops[2]) + && satisfies_constraint_Wc1 (ops[1])) + { + if (INTVAL (ops[avl_type_index]) == VLMAX) + return true; + /* AVL propagation PASS will transform FIXED-VLMAX with NUNITS < 32 + into NON-VLMAX with LEN = NUNITS. */ + else if (CONST_INT_P (ops[4]) + && known_eq (INTVAL (ops[4]), GET_MODE_NUNITS (mode))) + return true; + } + return false; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3d2c1c3ce8f..be5beb5ab64 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1724,10 +1724,7 @@ vse.v\t%3,%0%p1 vmv.v.v\t%0,%3 vmv.v.v\t%0,%3" - "&& register_operand (operands[0], mode) - && register_operand (operands[3], mode) - && satisfies_constraint_vu (operands[2]) - && INTVAL (operands[7]) == riscv_vector::VLMAX" + "&& riscv_vector::whole_reg_to_reg_move_p (operands, mode, 7)" [(set (match_dup 0) (match_dup 3))] "" [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov") @@ -1776,9 +1773,7 @@ vmmv.m\t%0,%3 vmclr.m\t%0 vmset.m\t%0" - "&& register_operand (operands[0], mode) - && register_operand (operands[3], mode) - && INTVAL (operands[5]) == riscv_vector::VLMAX" + "&& riscv_vector::whole_reg_to_reg_move_p (operands, mode, 5)" [(set (match_dup 0) (match_dup 3))] "" [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c new file mode 100644 index 00000000000..1b4bfd96481 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ + +#include "riscv_vector.h" +void +f (float x, float y, void *out) +{ + float f[4] = { x, x, x, y }; + vfloat32m1_t v = __riscv_vle32_v_f32m1 (f, 4); + __riscv_vse32_v_f32m1 (out, v, 4); +} + +/* { dg-final { scan-assembler-not {vmv} } } */