From patchwork Wed Jan 3 06:08:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 1881858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T4fSJ1g2Rz1ydb for ; Wed, 3 Jan 2024 17:09:20 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F3E693857BB2 for ; Wed, 3 Jan 2024 06:09:17 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-118.freemail.mail.aliyun.com (out30-118.freemail.mail.aliyun.com [115.124.30.118]) by sourceware.org (Postfix) with ESMTPS id 78DF83858C2C for ; Wed, 3 Jan 2024 06:08:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 78DF83858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 78DF83858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.118 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704262138; cv=none; b=po+H8QG0r2Kr1E7lGJS/rj5SUX3SuSCe5AxWQ2Crh7U+FuHH9Ja4dn9I6XrIbio7zTVEpy8nnHo55zI2lZnISTNNhFkE/+BNYAlBva8rgnkIef+0uWSr74BQgRrry41qdUzGF1W723KQyClkjRYi/yQk3tw09O2wWoeM33AETcI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704262138; c=relaxed/simple; bh=Ptm0wXvrES45niwmOJybJUoNMOmKExisR52hP/UyaX0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=u+LC3N0JWxNbORLs95+pQtGm5hCWIdg4cgt0//ttc0ui64zZMYBtANc/eaF6M4M7gRja0vsLHreebLyx0vlQdfsI6ksC993//0QVczfDXYpqzHxADp+JTJocHgUFj71C9jJeW1G+a+1r+WHWBpJUQp5eNrOtVHansfQYMO84CFY= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R211e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046060; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0VzstV4l_1704262127; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VzstV4l_1704262127) by smtp.aliyun-inc.com; Wed, 03 Jan 2024 14:08:50 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, "Jun Sha (Joshua)" , Jin Ma , Xianmiao Qu Subject: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. Date: Wed, 3 Jan 2024 14:08:37 +0800 Message-Id: <20240103060837.1684-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231229041943.1366-1-cooper.joshua@linux.alibaba.com> References: <20231229041943.1366-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-19.7 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, URIBL_BLACK, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. We only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function to add assembler insn code prefix/suffix. (th_asm_output_opcode): Thead function to add assembler insn code prefix/suffix. * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. * config/riscv/thead.cc (th_asm_output_opcode): Likewise gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/prefix.c: New test. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/config/riscv/riscv-protos.h | 2 ++ gcc/config/riscv/riscv.cc | 11 +++++++++++ gcc/config/riscv/riscv.h | 4 ++++ gcc/config/riscv/thead.cc | 13 +++++++++++++ .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 ++++++++++++ 5 files changed, 42 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 31049ef7523..71724dabdb5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -102,6 +102,7 @@ struct riscv_address_info { }; /* Routines implemented in riscv.cc. */ +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p); extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); extern int riscv_float_const_rtx_index_for_fli (rtx); @@ -717,6 +718,7 @@ extern void th_mempair_prepare_save_restore_operands (rtx[4], bool, int, HOST_WIDE_INT, int, HOST_WIDE_INT); extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); +extern const char *th_asm_output_opcode (FILE *asm_out_file, const char *p); #ifdef RTX_CODE extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0d1cbc5cb5f..51878797287 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5636,6 +5636,17 @@ riscv_get_v_regno_alignment (machine_mode mode) return lmul; } +/* Define ASM_OUTPUT_OPCODE to do anything special before + emitting an opcode. */ +const char * +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) +{ + if (TARGET_XTHEADVECTOR) + return th_asm_output_opcode (asm_out_file, p); + + return p; +} + /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 'h' Print the high-part relocation associated with OP, after stripping diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 6df9ec73c5e..c33361a254d 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use); asm_fprintf ((FILE), "%U%s", (NAME)); \ } while (0) +#undef ASM_OUTPUT_OPCODE +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ + (PTR) = riscv_asm_output_opcode(STREAM, PTR) + #define JUMP_TABLES_IN_TEXT_SECTION 0 #define CASE_VECTOR_MODE SImode #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 20353995931..dc3aed3904d 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -883,6 +883,19 @@ th_output_move (rtx dest, rtx src) return NULL; } +/* Define ASM_OUTPUT_OPCODE to do anything special before + emitting an opcode. */ +const char * +th_asm_output_opcode (FILE *asm_out_file, const char *p) +{ + /* We need to add th. prefix to all the xtheadvector + instructions here.*/ + if (current_output_insn != NULL && p[0] == 'v') + fputs ("th.", asm_out_file); + + return p; +} + /* Implement TARGET_PRINT_OPERAND_ADDRESS for XTheadMemIdx. */ bool diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c new file mode 100644 index 00000000000..eee727ef6b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */ + +#include "riscv_vector.h" + +vint32m1_t +prefix (vint32m1_t vx, vint32m1_t vy, size_t vl) +{ + return __riscv_vadd_vv_i32m1 (vx, vy, vl); +} + +/* { dg-final { scan-assembler {\mth\.v\M} } } */