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X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="398724951" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="398724951" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 00:26:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="752871596" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="752871596" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 21 Dec 2023 00:25:59 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id EF7C81005700; Thu, 21 Dec 2023 16:25:58 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com, gerald@pfeifer.com Subject: [gcc-wwwdocs PATCH v2] gcc-13/14: Mention recent update for x86_64 backend Date: Thu, 21 Dec 2023 16:25:58 +0800 Message-Id: <20231221082558.449203-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi all, This is the v2 patch for the wwwdocs change regarding to review. If there is no objection, I will push this change next Tuesday. Changes is v2: - Remove RAO-INT from Grand Ridge - Remove the mask register restriction for -mno-evex512 - Arrange the options alphabetically - Other minor text change Thx, Haochen Messages in v1: This patch will mention the following changes in wwwdocs for x86_64 backend: - AVX10.1 support - APX EGPR, PUSH2POP2, PPX and NDD support - Xeon Phi ISAs deprecated Also I adjust the words in x86_64 part for GCC 13. --- Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14. Also adjust documentation in GCC 13. --- htdocs/gcc-13/changes.html | 38 ++++++++++++++++++++------------------ htdocs/gcc-14/changes.html | 27 ++++++++++++++++++++++----- 2 files changed, 42 insertions(+), 23 deletions(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index d3bacc16..b4b1a39a 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -543,24 +543,28 @@ You may also want to check out our __bf16 type to x86 psABI. Users need to adjust their AVX512BF16-related source code when upgrading GCC12 to GCC13. -
  • New ISA extension support for Intel AVX-IFMA was added. - AVX-IFMA intrinsics are available via the -mavxifma +
  • New ISA extension support for Intel AMX-COMPLEX was added. + AMX-COMPLEX intrinsics are available via the -mamx-complex compiler switch.
    • -
  • New ISA extension support for Intel AVX-VNNI-INT8 was added. - AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8 +
  • New ISA extension support for Intel AMX-FP16 was added. + AMX-FP16 intrinsics are available via the -mamx-fp16 + compiler switch. +
    • +
  • New ISA extension support for Intel AVX-IFMA was added. + AVX-IFMA intrinsics are available via the -mavxifma compiler switch.
  • New ISA extension support for Intel AVX-NE-CONVERT was added. AVX-NE-CONVERT intrinsics are available via the -mavxneconvert compiler switch.
    • -
  • New ISA extension support for Intel CMPccXADD was added. - CMPccXADD intrinsics are available via the -mcmpccxadd +
  • New ISA extension support for Intel AVX-VNNI-INT8 was added. + AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8 compiler switch.
    • -
  • New ISA extension support for Intel AMX-FP16 was added. - AMX-FP16 intrinsics are available via the -mamx-fp16 +
  • New ISA extension support for Intel CMPccXADD was added. + CMPccXADD intrinsics are available via the -mcmpccxadd compiler switch.
  • New ISA extension support for Intel PREFETCHI was added. @@ -571,10 +575,6 @@ You may also want to check out our RAO-INT intrinsics are available via the -mraoint compiler switch.
    • -
  • New ISA extension support for Intel AMX-COMPLEX was added. - AMX-COMPLEX intrinsics are available via the -mamx-complex - compiler switch. -
  • GCC now supports the Intel CPU named Raptor Lake through -march=raptorlake. Raptor Lake is based on Alder Lake. @@ -585,13 +585,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Sierra Forest through -march=sierraforest. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD and UINTR ISA extensions. + Based on ISA extensions enabled on Alder Lake, the switch further enables + the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR + ISA extensions.
  • GCC now supports the Intel CPU named Grand Ridge through -march=grandridge. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD, UINTR and RAO-INT ISA extensions. + Grand Ridge is based on Sierra Forest.
  • GCC now supports the Intel CPU named Emerald Rapids through -march=emeraldrapids. @@ -599,11 +599,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Granite Rapids through -march=graniterapids. - The switch enables the AMX-FP16 and PREFETCHI ISA extensions. + Based on Sapphire Rapids, the switch further enables the AMX-FP16 and + PREFETCHI ISA extensions.
  • GCC now supports the Intel CPU named Granite Rapids D through -march=graniterapids-d. - The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions. + Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA + extensions.
  • GCC now supports AMD CPUs based on the znver4 core via -march=znver4. The switch makes GCC consider diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 24e6409a..4b83037a 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -320,8 +320,18 @@ a work-in-progress.

    IA-32/x86-64

    • New compiler option -m[no-]evex512 was added. - The compiler switch enables/disables 512 bit vector and 64 bit mask - register. It will be default on if AVX512F is enabled. + The compiler switch enables/disables 512-bit vector. + It will be default on if AVX512F is enabled. +
      • +
    • Part of new feature support for Intel APX was added, including EGPR, + NDD, PPX and PUSH2POP2. APX support is available via the + -mapxf compiler switch. +
      • +
    • New ISA extension support for Intel AVX10.1 was added. + AVX10.1 intrinsics are available via the -mavx10.1 or + -mavx10.1-256 compiler switch with 256-bit vector size + support. 512-bit vector size support for AVX10.1 intrinsics are + available via the -mavx10.1-512 compiler switch.
    • New ISA extension support for Intel AVX-VNNI-INT16 was added. AVX-VNNI-INT16 intrinsics are available via the -mavxvnniint16 @@ -346,13 +356,12 @@ a work-in-progress.

    • GCC now supports the Intel CPU named Clearwater Forest through -march=clearwaterforest. Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16, - SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions. - extensions. + PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
    • GCC now supports the Intel CPU named Arrow Lake through -march=arrowlake. Based on Alder Lake, the switch further enables the AVX-IFMA, - AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions. + AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions.
    • GCC now supports the Intel CPU named Arrow Lake S through -march=arrowlake-s. @@ -368,6 +377,14 @@ a work-in-progress.

      Based on Arrow Lake S, the switch further enables the PREFETCHI ISA extensions.
      • +
    • Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked + as deprecated. GCC will emit a warning when using the + -mavx5124fmaps, -mavx5124vnniw, + -mavx512er, -mavx512pf, + -mprefetchwt1, -march=knl, + -march=knm, -mtune=knl or -mtune=knm + compiler switches. Support will be removed in GCC 15. +