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X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="384769142" X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="384769142" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2023 23:02:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="19984228" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa001.jf.intel.com with ESMTP; 07 Dec 2023 23:02:52 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 34A421007829; Fri, 8 Dec 2023 15:02:50 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, gerald@pfeifer.com Subject: [gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend Date: Fri, 8 Dec 2023 15:02:50 +0800 Message-Id: <20231208070250.2837967-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi all, This patch will mention the following changes in wwwdocs for x86_64 backend: - AVX10.1 support - APX EGPR, PUSH2POP2, PPX and NDD support - Xeon Phi ISAs deprecated Also I adjust the words in x86_64 part for GCC 13. Ok for gcc-wwwdocs? Thx, Haochen Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14. Also adjust documentation in GCC 13. --- htdocs/gcc-13/changes.html | 14 ++++++++------ htdocs/gcc-14/changes.html | 18 ++++++++++++++++++ 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index 8ef3d639..e29ca72e 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -579,13 +579,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Sierra Forest through -march=sierraforest. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD and UINTR ISA extensions. + Based on ISA extensions enabled on Alder Lake, the switch further enables + the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, ENQCMD and UINTR + ISA extensions.
  • GCC now supports the Intel CPU named Grand Ridge through -march=grandridge. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, - ENQCMD, UINTR and RAO-INT ISA extensions. + Based on Sierra Forest, the switch further enables RAO-INT ISA extensions.
  • GCC now supports the Intel CPU named Emerald Rapids through -march=emeraldrapids. @@ -593,11 +593,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Granite Rapids through -march=graniterapids. - The switch enables the AMX-FP16, PREFETCHI ISA extensions. + Based on Sapphire Rapids, the switch further enables the AMX-FP16 and + PREFETCHI ISA extensions.
  • GCC now supports the Intel CPU named Granite Rapids D through -march=graniterapids-d. - The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions. + Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA + extensions.
  • GCC now supports AMD CPUs based on the znver4 core via -march=znver4. The switch makes GCC consider diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 6d7138f8..8590f735 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -296,6 +296,16 @@ a work-in-progress.

    USER_MSR intrinsics are available via the -muser_msr compiler switch.
    • +
  • New ISA extension support for Intel AVX10.1 was added. + AVX10.1 intrinsics are available via the -mavx10.1 or + -mavx10.1-256 compiler switch with 256 bit vector size + support. 512 bit vector size support for AVX10.1 intrinsics are + available via the -mavx10.1-512 compiler switch. +
    • +
  • Part of new feature support for Intel APX was added, including EGPR, + PUSH2POP2, PPX and NDD. APX features are available via the + -mapxf compiler switch. +
  • GCC now supports the Intel CPU named Clearwater Forest through -march=clearwaterforest. Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16, @@ -321,6 +331,14 @@ a work-in-progress.

    Based on Arrow Lake S, the switch further enables the PREFETCHI ISA extensions.
    • +
  • Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked + as deprecated. GCC will emit a warning when using the + -mavx5124fmaps, -mavx5124vnniw, + -mavx512er, -mavx512pf, + -mprefetchwt1, -march=knl, + -march=knm, -mtune=knl and -mtune=knm + compiler switch. The support will be removed in GCC 15. +