From patchwork Tue Dec 5 02:29:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 1871781 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=l9MVf2ox; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Skl7z3sx2z23mf for ; Tue, 5 Dec 2023 13:38:07 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3B1FC392A8DA for ; Tue, 5 Dec 2023 02:32:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 52DD83882124 for ; Tue, 5 Dec 2023 02:31:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52DD83882124 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 52DD83882124 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701743470; cv=none; b=aWsS8tc9+z53A0TM3Iujo+IwXc49DPX4iz8GQVF2yQhzo/13s2wftYYW7vg/IHM67K8hl5GR7ZYwVjN2TtjunBJ/lSrgJWFYfzLwpCRBtkyDtvri5R2L5c3xXLikrK4kzO4m1i6lpLiLFhdwq6EpiTK8kzyFZmgx7WHrMF7tLhs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701743470; c=relaxed/simple; bh=1R8R1T66Xd5tmZC/q/CB3N0p4deraFzMzBiiH5YWoV8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Ty9sFATxUPUFR13JR7CaoF/xDoWwH9HVcRLCAP2tzz/3iKqfCdXFkMG1Ikbc1G/81HYGbe/wz4tJi9+724B89vjRX4FL8mWAVMydqNrifRokQXajjwTR2emELgqtMyuiACHXlN1yB155fVHVR/1G/KqmdQagYZ/fXx9JrfZSIvY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mgamail.intel.com ([192.55.52.136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rALD5-0001YN-UO for gcc-patches@gcc.gnu.org; Mon, 04 Dec 2023 21:30:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701743455; x=1733279455; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1R8R1T66Xd5tmZC/q/CB3N0p4deraFzMzBiiH5YWoV8=; b=l9MVf2oxM0OS+j5fQBwZHWmyW7gxFNGrvOdt7oXyHLAQPcbk7eRIDVqB MTbfuL+zA1Uz+/zmDA+bNeqSy+U9ynHfjO5bO8VcHOuYr9AXG1rRRfZme 8GIKtHOtQ2j+zYntpNUa2eAE2OQpNwoFJZ+SzYlAj1pT5clLUXy68nZbN JmQs9v/CqXE8NpYnu+Ht48rxjFFnajkfarbCGwMuMnAvGk2miMMTmbut8 zMMWCE7k8R1ddkUOhNyq04J5DQ84QXbYJahKn1RUGOv1C2WJ6uTHEHAfW X426XnxfjMXNDwFJsstcYaJcPILNbY++Tub21yDvg0FpY9oeg+mHyGk1M Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10914"; a="373277776" X-IronPort-AV: E=Sophos;i="6.04,251,1695711600"; d="scan'208";a="373277776" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2023 18:29:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10914"; a="841275489" X-IronPort-AV: E=Sophos;i="6.04,251,1695711600"; d="scan'208";a="841275489" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 04 Dec 2023 18:29:49 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 39F0F1005665; Tue, 5 Dec 2023 10:29:48 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 02/17] [APX NDD] Restrict TImode register usage when NDD enabled Date: Tue, 5 Dec 2023 10:29:33 +0800 Message-Id: <20231205022948.504790-3-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231205022948.504790-1-hongyu.wang@intel.com> References: <20231205022948.504790-1-hongyu.wang@intel.com> MIME-Version: 1.0 Received-SPF: softfail client-ip=192.55.52.136; envelope-from=wwwhhhyyy333@gmail.com; helo=mgamail.intel.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Under APX NDD, previous TImode allocation will have issue that it was originally allocated using continuous pair, like rax:rdi, rdi:rdx. This will cause issue for all TImode NDD patterns. For NDD we will not assume the arithmetic operations like add have dependency between dest and src1, then write to 1st highpart rdi will be overrided by the 2nd lowpart rdi if 2nd lowpart rdi have different src as input, then the write to 1st highpart rdi will missed and cause miscompliation. To resolve this, under TARGET_APX_NDD we'd only allow register with even regno to be allocated with TImode, then TImode registers will be allocated with non-overlapping pairs. There could be some error for inline assembly if it forcely allocate __int128 with odd number general register. gcc/ChangeLog: * config/i386/i386.cc (ix86_hard_regno_mode_ok): Restrict even regno for TImode if APX NDD enabled. --- gcc/config/i386/i386.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 93a9cb556a5..3efeed396c4 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -20873,6 +20873,16 @@ ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return true; return !can_create_pseudo_p (); } + /* With TImode we previously have assumption that src1/dest will use same + register, so the allocation of highpart/lowpart can be consecutive, and + 2 TImode insn would held their low/highpart in continuous sequence like + rax:rdx, rdx:rcx. This will not work for APX_NDD since NDD allows + different registers as dest/src1, when writes to 2nd lowpart will impact + the writes to 1st highpart, then the insn will be optimized out. So for + TImode pattern if we support NDD form, the allowed register number should + be even to avoid such mixed high/low part override. */ + else if (TARGET_APX_NDD && mode == TImode) + return regno % 2 == 0; /* We handle both integer and floats in the general purpose registers. */ else if (VALID_INT_MODE_P (mode) || VALID_FP_MODE_P (mode))