diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c
new file mode 100644
index 00000000000..66361ad567d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+    vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+    vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+    vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c
new file mode 100644
index 00000000000..901e03bc181
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, uint32_t x)
+{
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+    vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tu (v3, v2, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, uint32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+    vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_m (mask, v3, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, uint32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+    vuint32m1_t v3 = __riscv_vdivu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vdivu_vx_u32m1_tumu (mask, v3, v2, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c
new file mode 100644
index 00000000000..651244f7a0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c
new file mode 100644
index 00000000000..25460cd3f17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, uint32_t x)
+{
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, uint32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, uint32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c
new file mode 100644
index 00000000000..651244f7a0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, 5, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, 5, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c
new file mode 100644
index 00000000000..25460cd3f17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, uint32_t x)
+{
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tu (v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tu (v3, v2, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, uint32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_m (mask, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_m (mask, v3, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, uint32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vuint32m1_t v = __riscv_vle32_v_u32m1 (in, 4);
+    vuint32m1_t v2 = __riscv_vle32_v_u32m1_tumu (mask, v, in, 4);
+    vuint32m1_t v3 = __riscv_vremu_vx_u32m1 (v2, x, 4);
+    vuint32m1_t v4 = __riscv_vremu_vx_u32m1_tumu (mask, v3, v2, x, 4);
+    __riscv_vse32_v_u32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c
new file mode 100644
index 00000000000..aca803f3930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, x, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_tu (v3, v2, x, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, x, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_m (mask, v3, x, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, x, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_tumu (mask, v3, v2, x, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c
new file mode 100644
index 00000000000..ce9261f67e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, -15, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_tu (v3, v2, -15, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, -15, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_m (mask, v3, -15, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, -15, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_tumu (mask, v3, v2, -15, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c
new file mode 100644
index 00000000000..3adb7ae8f79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, 16, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_tu (v3, v2, 16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, 16, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_m (mask, v3, 16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vsub_vx_i32m1 (v2, 16, 4);
+    vint32m1_t v4 = __riscv_vsub_vx_i32m1_tumu (mask, v3, v2, 16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c
new file mode 100644
index 00000000000..995b52130cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 17, 4);
+    vint32m1_t v4 = __riscv_vadd_vx_i32m1_tu (v3, v2, 17, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 17, 4);
+    vint32m1_t v4 = __riscv_vadd_vx_i32m1_m (mask, v3, 17, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vadd_vx_i32m1 (v2, 17, 4);
+    vint32m1_t v4 = __riscv_vadd_vx_i32m1_tumu (mask, v3, v2, 17, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c
new file mode 100644
index 00000000000..7c4b1e78ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, x, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, x, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, x, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, x, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, x, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, x, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c
new file mode 100644
index 00000000000..b971a9af222
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, -16, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, -16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, -16, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, -16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, -16, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, -16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c
new file mode 100644
index 00000000000..ae23fa67f02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 15, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, 15, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 15, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, 15, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**	th.vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 15, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, 15, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c
new file mode 100644
index 00000000000..120230d1f2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f1 (void * in, void *out, int32_t x)
+{
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 16, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tu (v3, v2, 16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f2 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 16, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_m (mask, v3, 16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+**  ...
+**	th.vle.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+**  ...
+**	th.vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
+**	th.vse.v\tv[0-9]+,0\([a-x0-9]+\)
+**	ret
+*/
+void f3 (void * in, void *out, int32_t x)
+{
+    vbool32_t mask = *(vbool32_t*)in;
+    asm volatile ("":::"memory");
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+    vint32m1_t v3 = __riscv_vrsub_vx_i32m1 (v2, 16, 4);
+    vint32m1_t v4 = __riscv_vrsub_vx_i32m1_tumu (mask, v3, v2, 16, 4);
+    __riscv_vse32_v_i32m1 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c
new file mode 100644
index 00000000000..cec8a0b8012
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c
@@ -0,0 +1,123 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcxtheadvector -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f0:
+**  ...
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**  ...
+**	ret
+*/
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, -16, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, -16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f1:
+**  ...
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 15, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 15, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 16, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f4:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f5:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f6:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c
new file mode 100644
index 00000000000..7210890f20f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f0:
+**  ...
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
+**  ...
+**	ret
+*/
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, -16, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, -16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f1:
+**  ...
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**	th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 15, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 15, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 16, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1 (v3, 0xAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c
new file mode 100644
index 00000000000..0351e452d5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */
+#include "riscv_th_vector.h"
+
+void f (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */
+/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-not {th.vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c
new file mode 100644
index 00000000000..3b849e906db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */
+#include "riscv_th_vector.h"
+
+void f (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */
+/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-not {th.vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c
new file mode 100644
index 00000000000..4a18a410252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */
+#include "riscv_th_vector.h"
+
+void f (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */
+/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-not {th.vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c
new file mode 100644
index 00000000000..6713316fcab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32 -O3" } */
+#include "riscv_th_vector.h"
+
+void f (void * in, void *out, int32_t x, int n)
+{
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4);
+    vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4);
+    vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, x, 4);
+    vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, x, 4);
+    __riscv_vse64_v_i64m1 (out + i + 2, v4, 4);
+  }
+}
+
+/* { dg-final { scan-assembler-times {th.vlse\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */
+/* { dg-final { scan-assembler-times {th.vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-not {th.vmv} } } */
