From patchwork Fri Nov 17 08:52:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 1864991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SWrKZ3j3Hz1yS7 for ; Fri, 17 Nov 2023 19:53:38 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AFC663857BA6 for ; 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d=sourceware.org; s=key; t=1700211203; c=relaxed/simple; bh=cnKC1QEZJPIsiteENQRAnZKF7XVHQAdDwHGoPL6RRYE=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=OpnEDWjJ/Cmsekl/HoWZrm7f6QVikkPFmooZs9wdeEl25SnUjnE8TO5OGZCReL1ybks9wwFMAL5DvvpuuhFCP0KOXZRIIRPhd0oqYF3BiQePQlsfNdA+j1GoV8lznqQMilgX5LumfeS0M/9nm0meFNlwECCoqGAeA0kgUInCufM= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R511e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046050; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VwZPp0h_1700211191; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VwZPp0h_1700211191) by smtp.aliyun-inc.com; Fri, 17 Nov 2023 16:53:15 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, "Jun Sha (Joshua)" Subject: [PATCH 1/9] RISC-V: minimal support for xtheadvector Date: Fri, 17 Nov 2023 16:52:53 +0800 Message-Id: <20231117085253.2764-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20231117081955.2395-1-cooper.joshua@linux.alibaba.com> References: <20231117081955.2395-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.7 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): : Add new vendor extension. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add test marco. * config/riscv/riscv.opt: Add new mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test. * gcc.target/riscv/rvv/xtheadvector.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 10 ++++++++++ gcc/config/riscv/riscv-c.cc | 4 ++++ gcc/config/riscv/riscv.opt | 2 ++ .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c | 13 +++++++++++++ 5 files changed, 40 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 526dbb7603b..914924171fd 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -75,6 +75,8 @@ static const riscv_implied_info_t riscv_implied_info[] = {"v", "zvl128b"}, {"v", "zve64d"}, + {"xtheadvector", "zvl128b"}, + {"xtheadvector", "zve64d"}, {"zve32f", "f"}, {"zve64f", "f"}, @@ -325,6 +327,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0}, {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1495,6 +1498,10 @@ riscv_subset_list::parse (const char *arch, location_t loc) error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point " "extensions", arch); + if (subset_list->lookup ("v") && subset_list->lookup ("xtheadvector")) + error_at (loc, "%<-march=%s%>: xtheadvector conflicts with vector " + "extensions", arch); + /* 'H' hypervisor extension requires base ISA with 32 registers. */ if (subset_list->lookup ("e") && subset_list->lookup ("h")) error_at (loc, "%<-march=%s%>: h extension requires i extension", arch); @@ -1680,6 +1687,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, + {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR}, + {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V}, + {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR}, {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index b7f9ba204f7..184fff905b2 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -137,6 +137,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) riscv_ext_version_value (0, 11)); } + if (TARGET_XTHEADVECTOR) + builtin_define_with_int_value ("__riscv_th_v_intrinsic", + riscv_ext_version_value (0, 11)); + /* Define architecture extension test macros. */ builtin_define_with_int_value ("__riscv_arch_test", 1); diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 70d78151cee..72857aea352 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) Mask(XTHEADSYNC) Var(riscv_xthead_subext) +Mask(XTHEADVECTOR) Var(riscv_xthead_subext) + TargetVariable int riscv_xventana_subext diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c new file mode 100644 index 00000000000..1c764241db6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */ + +int main () { + +#if __riscv_th_v_intrinsic != 11000 +#error "__riscv_th_v_intrinsic" +#endif + + return 0; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c new file mode 100644 index 00000000000..d52921e1314 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */ + +#ifndef __riscv_xtheadvector +#error "Feature macro not defined" +#endif + +int +foo (int a) +{ + return a; +} \ No newline at end of file