@@ -75,6 +75,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"v", "zvl128b"},
{"v", "zve64d"},
+ {"xtheadvector", "zvl128b"},
+ {"xtheadvector", "zve64d"},
{"zve32f", "f"},
{"zve64f", "f"},
@@ -325,6 +327,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1495,6 +1498,10 @@ riscv_subset_list::parse (const char *arch, location_t loc)
error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
"extensions", arch);
+ if (subset_list->lookup ("v") && subset_list->lookup ("xtheadvector"))
+ error_at (loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+ "extensions", arch);
+
/* 'H' hypervisor extension requires base ISA with 32 registers. */
if (subset_list->lookup ("e") && subset_list->lookup ("h"))
error_at (loc, "%<-march=%s%>: h extension requires i extension", arch);
@@ -1680,6 +1687,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+ {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V},
+ {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR},
{"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
@@ -137,6 +137,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
riscv_ext_version_value (0, 11));
}
+ if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+ riscv_ext_version_value (0, 11));
+
/* Define architecture extension test macros. */
builtin_define_with_int_value ("__riscv_arch_test", 1);
@@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
Mask(XTHEADSYNC) Var(riscv_xthead_subext)
+Mask(XTHEADVECTOR) Var(riscv_xthead_subext)
+
TargetVariable
int riscv_xventana_subext
new file mode 100644
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */
+
+int main () {
+
+#if __riscv_th_v_intrinsic != 11000
+#error "__riscv_th_v_intrinsic"
+#endif
+
+ return 0;
+}
\ No newline at end of file
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadvector
+#error "Feature macro not defined"
+#endif
+
+int
+foo (int a)
+{
+ return a;
+}
\ No newline at end of file