diff mbox series

[4/5] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa

Message ID 20231116131836.504699-6-xry111@xry111.site
State New
Headers show
Series LoongArch: Initial LA664 support | expand

Commit Message

Xi Ruoyao Nov. 16, 2023, 1:18 p.m. UTC 
This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other".  Thus
we can omit the "load-load" barrier dbar 0x700.

This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
	print dbar 0x700 if TARGET_LD_SEQ_SA.
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 6f89d468795..c6eec2345a9 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6061,7 +6061,7 @@  loongarch_print_operand (FILE *file, rtx op, int letter)
       if (loongarch_cas_failure_memorder_needs_acquire (
 	    memmodel_from_int (INTVAL (op))))
 	fputs ("dbar\t0b10100", file);
-      else
+      else if (!TARGET_LD_SEQ_SA)
 	fputs ("dbar\t0x700", file);
       break;