From patchwork Fri Nov 10 08:14:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1862361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=hqb7t5UH; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SRWpB4z3qz1yQy for ; Fri, 10 Nov 2023 19:14:58 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 73A423858407 for ; Fri, 10 Nov 2023 08:14:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by sourceware.org (Postfix) with ESMTPS id EC6813858D1E for ; Fri, 10 Nov 2023 08:14:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC6813858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EC6813858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699604084; cv=none; b=OUHznVD2Kvzp+PNizkpUdmHrxtlw8egQgwiaaC09NqCRNK8wmwGMEAdqxyquZupwxXzntqWBPmfeq5DALl/biUYeeBAhBUu7f3O0+hgroYs1FpyWbVn+prI+rdndvTNFjz2iR2Cos3mVasBv9hu/wttRsackzIyHT3OyiKyGUuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699604084; c=relaxed/simple; bh=E5nxdYNTcO5ny1BXQHWQU2RaUOZHNjrAGtQvHf5nMis=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=L/wDohr6ZjhGs0lcZB9zsXM019uBaoUSyHRmgcQC5mrvJNkQyb8/xuVwcv5QOZ2kEsPk8mJjLT6W798jpkMnYxoAKEW0aN90ViNtUUO5KPOUNm4WybVMVIxsM8k/dcIsu8XR0IZM1ahKtKCcdSiVqwxKteJ2nKQc0iL9kyWKRlk= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699604082; x=1731140082; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=E5nxdYNTcO5ny1BXQHWQU2RaUOZHNjrAGtQvHf5nMis=; b=hqb7t5UHzgb1XnpA8zKJ9RYDnKWf8/NJPQFNYpaDadPjVlUSnwNyZY1Z uK3uqafyxsPmzzRIa/WrpESEzaKJPyAyTN9pfuPzL6dp93Oz8dJc0oo1k mnpWUh6pplT33+APohs+f9UzExfjgGER5e2U4UdzAtjS8v8nUPM/dG8bl E9QPHC9Izfnz0FKXK0q4YKvlt5F2ao4TvpzqeMKTFyl8ePhW9iqCm2Ac8 5UoJSK5coFm7U5C2uvRpfjWAQAZl63knZW04Er6PGhdp7I2voCY6LVTPY +CIjA2wA2Yv16sfbGorW925WIJ3MP+r2AIDXqFe+Cisa6vwF5PsRqqcX3 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10889"; a="8804984" X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="8804984" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2023 00:14:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10889"; a="880911663" X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="880911663" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 10 Nov 2023 00:14:37 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id D6084100567E; Fri, 10 Nov 2023 16:14:36 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec Date: Fri, 10 Nov 2023 16:14:35 +0800 Message-Id: <20231110081435.3963830-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The internal-fn has support the FLOATN already. This patch would like to re-enable the vector HFmode for the autovec for below standard name mode iterators. 1. lrint 2. llround For now the vector HFmodes are disabled to limit the impact, and the underlying FP16 rint/round autovec will enable this one by one. gcc/ChangeLog: * config/riscv/autovec.md: Disable vector HFmode for rint, round, ceil and floor. * config/riscv/vector-iterators.md: Add vector HFmode for rint, round, ceil and floor mode iterator. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/autovec.md | 26 +++++++----- gcc/config/riscv/vector-iterators.md | 59 +++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 12 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 33722ea1139..a199caabf87 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2443,12 +2443,11 @@ (define_expand "roundeven2" } ) -;; Add mode_size equal check as we opened the modes for different sizes. -;; The check will be removed soon after related codegen implemented (define_expand "lrint2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lrint (operands[0], operands[1], mode, mode); DONE; @@ -2458,7 +2457,8 @@ (define_expand "lrint2" (define_expand "lrint2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lrint (operands[0], operands[1], mode, mode); DONE; @@ -2468,7 +2468,8 @@ (define_expand "lrint2" (define_expand "lround2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lround (operands[0], operands[1], mode, mode); DONE; @@ -2478,7 +2479,8 @@ (define_expand "lround2" (define_expand "lround2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lround (operands[0], operands[1], mode, mode); DONE; @@ -2488,7 +2490,8 @@ (define_expand "lround2" (define_expand "lceil2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lceil (operands[0], operands[1], mode, mode); DONE; @@ -2498,7 +2501,8 @@ (define_expand "lceil2" (define_expand "lceil2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lceil (operands[0], operands[1], mode, mode); DONE; @@ -2508,7 +2512,8 @@ (define_expand "lceil2" (define_expand "lfloor2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode, mode); DONE; @@ -2518,7 +2523,8 @@ (define_expand "lfloor2" (define_expand "lfloor2" [(match_operand: 0 "register_operand") (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && GET_MODE_INNER (mode) != HFmode" { riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode, mode); DONE; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index e80eaedc4b3..f2d9f60b631 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -3221,15 +3221,20 @@ (define_mode_attr vnnconvert [ ;; V_F2SI_CONVERT: (HF, SF, DF) => SI ;; V_F2DI_CONVERT: (HF, SF, DF) => DI ;; -;; HF requires additional support from internal function, aka -;; gcc/internal-fn.def, remove HF shortly until the middle-end is ready. (define_mode_attr V_F2SI_CONVERT [ + (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI") + (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI") + (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI") (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") (RVVM1DF "RVVMF2SI") + (V1HF "V1SI") (V2HF "V2SI") (V4HF "V4SI") (V8HF "V8SI") (V16HF "V16SI") + (V32HF "V32SI") (V64HF "V64SI") (V128HF "V128SI") (V256HF "V256SI") + (V512HF "V512SI") (V1024HF "V1024SI") + (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI") (V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI") (V512SF "V512SI") (V1024SF "V1024SI") @@ -3240,12 +3245,19 @@ (define_mode_attr V_F2SI_CONVERT [ ]) (define_mode_attr v_f2si_convert [ + (RVVM4HF "rvvm8si") (RVVM2HF "rvvm4si") (RVVM1HF "rvvm2si") + (RVVMF2HF "rvvm1si") (RVVMF4HF "rvvmf2si") + (RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si") (RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si") (RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si") (RVVM1DF "rvvmf2si") + (V1HF "v1si") (V2HF "v2si") (V4HF "v4si") (V8HF "v8si") (V16HF "v16si") + (V32HF "v32si") (V64HF "v64si") (V128HF "v128si") (V256HF "v256si") + (V512HF "v512si") (V1024HF "v1024si") + (V1SF "v1si") (V2SF "v2si") (V4SF "v4si") (V8SF "v8si") (V16SF "v16si") (V32SF "v32si") (V64SF "v64si") (V128SF "v128si") (V256SF "v256si") (V512SF "v512si") (V1024SF "v1024si") @@ -3256,6 +3268,9 @@ (define_mode_attr v_f2si_convert [ ]) (define_mode_iterator V_VLS_F_CONVERT_SI [ + (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") + (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") @@ -3265,6 +3280,18 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [ (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") + (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") + (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") + (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") + (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") + (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") + (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32") (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32") (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32") @@ -3290,12 +3317,19 @@ (define_mode_iterator V_VLS_F_CONVERT_SI [ ]) (define_mode_attr V_F2DI_CONVERT [ + (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI") + (RVVMF4HF "RVVM1DI") + (RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI") (RVVMF2SF "RVVM1DI") (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI") + (V1HF "V1DI") (V2HF "V2DI") (V4HF "V4DI") (V8HF "V8DI") (V16HF "V16DI") + (V32HF "V32DI") (V64HF "V64DI") (V128HF "V128DI") (V256HF "V256DI") + (V512HF "V512DI") + (V1SF "V1DI") (V2SF "V2DI") (V4SF "V4DI") (V8SF "V8DI") (V16SF "V16DI") (V32SF "V32DI") (V64SF "V64DI") (V128SF "V128DI") (V256SF "V256DI") (V512SF "V512DI") @@ -3306,12 +3340,19 @@ (define_mode_attr V_F2DI_CONVERT [ ]) (define_mode_attr v_f2di_convert [ + (RVVM2HF "rvvm8di") (RVVM1HF "rvvm4di") (RVVMF2HF "rvvm2di") + (RVVMF4HF "rvvm1di") + (RVVM4SF "rvvm8di") (RVVM2SF "rvvm4di") (RVVM1SF "rvvm2di") (RVVMF2SF "rvvm1di") (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di") (RVVM1DF "rvvm1di") + (V1HF "v1di") (V2HF "v2di") (V4HF "v4di") (V8HF "v8di") (V16HF "v16di") + (V32HF "v32di") (V64HF "v64di") (V128HF "v128di") (V256HF "v256di") + (V512HF "v512di") + (V1SF "v1di") (V2SF "v2di") (V4SF "v4di") (V8SF "v8di") (V16SF "v16di") (V32SF "v32di") (V64SF "v64di") (V128SF "v128di") (V256SF "v256di") (V512SF "v512di") @@ -3322,6 +3363,9 @@ (define_mode_attr v_f2di_convert [ ]) (define_mode_iterator V_VLS_F_CONVERT_DI [ + (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") @@ -3329,6 +3373,17 @@ (define_mode_iterator V_VLS_F_CONVERT_DI [ (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") + (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") + (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") + (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") + (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") + (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32") (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32") (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")