From patchwork Sat Oct 28 02:05:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1856459 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SHND253Jmz1yQ4 for ; Sat, 28 Oct 2023 13:05:36 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A67E8385F023 for ; Sat, 28 Oct 2023 02:05:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id A01A33858D38 for ; Sat, 28 Oct 2023 02:05:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A01A33858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A01A33858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698458721; cv=none; b=WFNmD+WLKy9n40J6YSxfUvah1mZdeIOH/nzPUphjaRK7juWkioUuEWICwseoT4HAh/DL0eGEU+KlaDjzPZCHhjohEYOqxXxl/6cdo6UHwDRd4Z/zRYS3u+M+NCeedqyyTvUMwcl+k5VmqCEnI9P4QwOxEBelrMOA27BkxshW9p4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698458721; c=relaxed/simple; bh=8sM21RdmH9yZWkXNDcfPNXqk6rLRog6UBoKLAzqrM+k=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=kYAZQMzVamwf9fxNkrUdSYs9mxPo9VyWFckvcEp1tH9fKwMDDqsuu2euKmc1CZPtuquG5/ETdCYfeXNFqLoYaKqHmcg/E9ndFU6n56AXgq33yKTkgen5PWpb+s+Mbyid7eoi6Xm82E1BlFoDCDouJUJ61OwP9CaUHJexYR4W1Js= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp69t1698458710tl95hu7b Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 28 Oct 2023 10:05:08 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: abxxcdK0JW6KVfIoHxlDPwn0vkJAEEH15dYl+sLMzhQklr3dYBZNFtT+yzORn Zxog2/zyUVhps7hDlBP+vWjjR9SuMBTo/UgxR0pTQCF494I5IH9gWR9WNxUbg6fRMQtXtlR WCTDLzkGoMGvJl8sJAMqqlMZgj+h5QsR4kTBFAs5LKctKl1ifoURKaJrkERyJ5FH82DrY/W ObFZCSXJomNRFx4nhU/pid1TCxh0Ue+Os+EPQcrjEsxWOqPNI4vB8BJTL4rugdgqDVtA3S6 sGR3ycnSBmbUtt3dEiH4K2RnPR8RynuTVlRYUsgCdGX03qgyfpIjJVhoNCltsFcEHiWj6VC +qVRttQ1sBz/ZqE2Kk9wXCxi18/hjvyOD4A1lozQC+q39lVe4rKYPob4bOOWA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3416550543295755182 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 Date: Sat, 28 Oct 2023 10:05:07 +0800 Message-Id: <20231028020507.1934834-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org sew64_scalar_helper is handling SEW64 vx instruction pattern on RV32 system. According to RVV ISA, we can directly use vx instruction of SEW64 on RV32 system since RV32 GR reg is 32bit. Consider this following case: vsetvl e64m1 vadd.vx v,v,x will be transform by sew64_scalar_helper: vsetvl e64m1 sw sw vlse v vadd.vv This bug is reported by Robin. (insn 143 179 230 9 (set (reg:SI 15 a5 [234]) (unspec:SI [ (const_int 64 [0x40]) ] UNSPEC_VLMAX)) 751 {vlmax_avlsi} (expr_list:REG_EQUIV (unspec:SI [ (const_int 64 [0x40]) ] UNSPEC_VLMAX) (nil))) (insn 230 143 78 9 (parallel [ (set (reg:SI 66 vl) (unspec:SI [ (reg:SI 15 a5 [234]) (const_int 64 [0x40]) (const_int 0 [0]) ] UNSPEC_VSETVL)) (set (reg:SI 67 vtype) (unspec:SI [ (const_int 64 [0x40]) (const_int 0 [0]) (const_int 1 [0x1]) repeated x2 ] UNSPEC_VSETVL)) ]) "bug.c":14:14 discrim 1 1469 {vsetvl_discard_resultsi} (nil)) (insn 78 230 84 9 (set (reg:RVVM1DI 102 v6 [203]) (if_then_else:RVVM1DI (unspec:RVVMF64BI [ (const_vector:RVVMF64BI repeat [ (const_int 1 [0x1]) ]) (const_int 0 [0]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (vec_duplicate:RVVM1DI (mem/u/c:DI (reg/f:SI 29 t4 [230]) [0 S8 A64])) (unspec:RVVM1DI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF))) "bug.c":14:14 discrim 1 1872 {*pred_broadcastrvvm1di} (expr_list:REG_DEAD (reg/f:SI 29 t4 [230]) (nil))) The root cause of this is because we missed VLMAX handling since the codes was invented long time ago (Callers always intrinsics codes, no VLMAX situation). Now, all following bugs are fixed after this patch: FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test gcc/ChangeLog: * config/riscv/riscv-protos.h (sew64_scalar_helper): Fix bug. * config/riscv/riscv-v.cc (sew64_scalar_helper): Ditto. * config/riscv/vector.md: Ditto. --- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-v.cc | 8 +++-- gcc/config/riscv/vector.md | 54 ++++++++++++++++++++++----------- 3 files changed, 43 insertions(+), 21 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 2926d5d50d5..150b61bb5b5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -490,7 +490,7 @@ void expand_vec_lceil (rtx, rtx, machine_mode, machine_mode); void expand_vec_lfloor (rtx, rtx, machine_mode, machine_mode); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, - bool, void (*)(rtx *, rtx)); + bool, void (*)(rtx *, rtx), enum avl_type); rtx gen_scalar_move_mask (machine_mode); rtx gen_no_side_effects_vsetvl_rtx (machine_mode, rtx, rtx); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 53991cc1090..ee631404b44 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1641,7 +1641,7 @@ has_vi_variant_p (rtx_code code, rtx x) bool sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl, machine_mode vector_mode, bool has_vi_variant_p, - void (*emit_vector_func) (rtx *, rtx)) + void (*emit_vector_func) (rtx *, rtx), enum avl_type type) { machine_mode scalar_mode = GET_MODE_INNER (vector_mode); if (has_vi_variant_p) @@ -1671,7 +1671,11 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl, rtx tmp = gen_reg_rtx (vector_mode); rtx ops[] = {tmp, *scalar_op}; - emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), UNARY_OP, ops, vl); + if (type == VLMAX) + emit_vlmax_insn (code_for_pred_broadcast (vector_mode), UNARY_OP, ops); + else + emit_nonvlmax_insn (code_for_pred_broadcast (vector_mode), UNARY_OP, ops, + vl); emit_vector_func (operands, tmp); return true; diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cea3dbf37a6..c4c136cb5d2 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1779,7 +1779,8 @@ emit_insn (gen_pred_merge (operands[0], operands[1], operands[2], boardcast_scalar, operands[4], operands[5], operands[6], operands[7])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[7]))) DONE; }) @@ -2537,7 +2538,8 @@ emit_insn (gen_pred_ (operands[0], operands[1], operands[2], operands[3], boardcast_scalar, operands[5], operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -2612,7 +2614,8 @@ emit_insn (gen_pred_ (operands[0], operands[1], operands[2], operands[3], boardcast_scalar, operands[5], operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -2687,7 +2690,8 @@ emit_insn (gen_pred_sub (operands[0], operands[1], operands[2], boardcast_scalar, operands[3], operands[5], operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -2804,7 +2808,8 @@ emit_insn (gen_pred_mulh (operands[0], operands[1], operands[2], operands[3], boardcast_scalar, operands[5], operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -2978,7 +2983,8 @@ emit_insn (gen_pred_adc (operands[0], operands[1], operands[2], boardcast_scalar, operands[4], operands[5], operands[6], operands[7])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[7]))) DONE; }) @@ -3061,7 +3067,8 @@ emit_insn (gen_pred_sbc (operands[0], operands[1], operands[2], boardcast_scalar, operands[4], operands[5], operands[6], operands[7])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[7]))) DONE; }) @@ -3218,7 +3225,8 @@ [] (rtx *operands, rtx boardcast_scalar) { emit_insn (gen_pred_madc (operands[0], operands[1], boardcast_scalar, operands[3], operands[4], operands[5])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[5]))) DONE; }) @@ -3287,7 +3295,8 @@ [] (rtx *operands, rtx boardcast_scalar) { emit_insn (gen_pred_msbc (operands[0], operands[1], boardcast_scalar, operands[3], operands[4], operands[5])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[5]))) DONE; }) @@ -3429,7 +3438,8 @@ [] (rtx *operands, rtx boardcast_scalar) { emit_insn (gen_pred_madc_overflow (operands[0], operands[1], boardcast_scalar, operands[3], operands[4])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[4]))) DONE; }) @@ -3495,7 +3505,8 @@ [] (rtx *operands, rtx boardcast_scalar) { emit_insn (gen_pred_msbc_overflow (operands[0], operands[1], boardcast_scalar, operands[3], operands[4])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[4]))) DONE; }) @@ -4006,7 +4017,8 @@ emit_insn (gen_pred_ (operands[0], operands[1], operands[2], operands[3], boardcast_scalar, operands[5], operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -4081,7 +4093,8 @@ emit_insn (gen_pred_ (operands[0], operands[1], operands[2], operands[3], boardcast_scalar, operands[5], operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -4226,7 +4239,8 @@ emit_insn (gen_pred_ (operands[0], operands[1], operands[2], operands[3], boardcast_scalar, operands[5], operands[6], operands[7], operands[8], operands[9])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -4692,7 +4706,8 @@ emit_insn (gen_pred_cmp (operands[0], operands[1], operands[2], operands[3], operands[4], boardcast_scalar, operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -4724,7 +4739,8 @@ emit_insn (gen_pred_cmp (operands[0], operands[1], operands[2], operands[3], operands[4], boardcast_scalar, operands[6], operands[7], operands[8])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[8]))) DONE; }) @@ -5347,7 +5363,8 @@ emit_insn (gen_pred_mul_plus (operands[0], operands[1], boardcast_scalar, operands[3], operands[4], operands[5], operands[6], operands[7], operands[8], operands[9])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[9]))) DONE; }) @@ -5644,7 +5661,8 @@ emit_insn (gen_pred_minus_mul (operands[0], operands[1], boardcast_scalar, operands[3], operands[4], operands[5], operands[6], operands[7], operands[8], operands[9])); - })) + }, + (riscv_vector::avl_type) INTVAL (operands[9]))) DONE; })