RISC-V: Export some functions from riscv-vsetvl to riscv-v

Address kito's comments of AVL propagation patch.

Export the functions that are not only used by VSETVL PASS but also AVL propagation PASS.

No functionality change.
gcc/ChangeLog:

	* config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl to riscv-v
	(tail_agnostic_p): Ditto.
	(validate_change_or_fail): Ditto.
	(nonvlmax_avl_type_p): Ditto.
	(vlmax_avl_p): Ditto.
	(get_sew): Ditto.
	(enum vlmul_type): Ditto.
	(count_regno_occurrences): Ditto.
	* config/riscv/riscv-v.cc (has_vl_op): Ditto.
	(get_default_ta): Ditto.
	(tail_agnostic_p): Ditto.
	(validate_change_or_fail): Ditto.
	(nonvlmax_avl_type_p): Ditto.
	(vlmax_avl_p): Ditto.
	(get_sew): Ditto.
	(enum vlmul_type): Ditto.
	(get_vlmul): Ditto.
	(count_regno_occurrences): Ditto.
	* config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto.
	(has_vl_op): Ditto.
	(get_sew): Ditto.
	(get_vlmul): Ditto.
	(get_default_ta): Ditto.
	(tail_agnostic_p): Ditto.
	(count_regno_occurrences): Ditto.
	(validate_change_or_fail): Ditto.

---
 gcc/config/riscv/riscv-protos.h  |  8 +++
 gcc/config/riscv/riscv-v.cc      | 83 ++++++++++++++++++++++++++++++++
 gcc/config/riscv/riscv-vsetvl.cc | 70 ---------------------------
 3 files changed, 91 insertions(+), 70 deletions(-)

LGTM, but plz mention it's NFC in the title, no v2 needed :)

On Wed, Oct 25, 2023 at 5:03 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> Address kito's comments of AVL propagation patch.
>
> Export the functions that are not only used by VSETVL PASS but also AVL propagation PASS.
>
> No functionality change.
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl to riscv-v
>         (tail_agnostic_p): Ditto.
>         (validate_change_or_fail): Ditto.
>         (nonvlmax_avl_type_p): Ditto.
>         (vlmax_avl_p): Ditto.
>         (get_sew): Ditto.
>         (enum vlmul_type): Ditto.
>         (count_regno_occurrences): Ditto.
>         * config/riscv/riscv-v.cc (has_vl_op): Ditto.
>         (get_default_ta): Ditto.
>         (tail_agnostic_p): Ditto.
>         (validate_change_or_fail): Ditto.
>         (nonvlmax_avl_type_p): Ditto.
>         (vlmax_avl_p): Ditto.
>         (get_sew): Ditto.
>         (enum vlmul_type): Ditto.
>         (get_vlmul): Ditto.
>         (count_regno_occurrences): Ditto.
>         * config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto.
>         (has_vl_op): Ditto.
>         (get_sew): Ditto.
>         (get_vlmul): Ditto.
>         (get_default_ta): Ditto.
>         (tail_agnostic_p): Ditto.
>         (count_regno_occurrences): Ditto.
>         (validate_change_or_fail): Ditto.
>
> ---
>  gcc/config/riscv/riscv-protos.h  |  8 +++
>  gcc/config/riscv/riscv-v.cc      | 83 ++++++++++++++++++++++++++++++++
>  gcc/config/riscv/riscv-vsetvl.cc | 70 ---------------------------
>  3 files changed, 91 insertions(+), 70 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index fffd9cd0b8a..668d75043ca 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -560,6 +560,14 @@ bool cmp_lmul_gt_one (machine_mode);
>  bool gather_scatter_valid_offset_mode_p (machine_mode);
>  bool vls_mode_valid_p (machine_mode);
>  bool vlmax_avl_type_p (rtx_insn *);
> +bool has_vl_op (rtx_insn *);
> +bool tail_agnostic_p (rtx_insn *);
> +void validate_change_or_fail (rtx, rtx *, rtx, bool);
> +bool nonvlmax_avl_type_p (rtx_insn *);
> +bool vlmax_avl_p (rtx);
> +uint8_t get_sew (rtx_insn *);
> +enum vlmul_type get_vlmul (rtx_insn *);
> +int count_regno_occurrences (rtx_insn *, unsigned int);
>  }
>
>  /* We classify builtin types into two classes:
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index d439ec06af0..3fe8125801b 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4447,4 +4447,87 @@ vlmax_avl_type_p (rtx_insn *rinsn)
>    return INTVAL (avl_type) == VLMAX;
>  }
>
> +/* Return true if it is an RVV instruction depends on VL global
> +   status register.  */
> +bool
> +has_vl_op (rtx_insn *rinsn)
> +{
> +  return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn);
> +}
> +
> +/* Get default tail policy.  */
> +static bool
> +get_default_ta ()
> +{
> +  /* For the instruction that doesn't require TA, we still need a default value
> +     to emit vsetvl. We pick up the default value according to prefer policy. */
> +  return (bool) (get_prefer_tail_policy () & 0x1
> +                || (get_prefer_tail_policy () >> 1 & 0x1));
> +}
> +
> +/* Helper function to get TA operand.  */
> +bool
> +tail_agnostic_p (rtx_insn *rinsn)
> +{
> +  /* If it doesn't have TA, we return agnostic by default.  */
> +  extract_insn_cached (rinsn);
> +  int ta = get_attr_ta (rinsn);
> +  return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta);
> +}
> +
> +/* Change insn and Assert the change always happens.  */
> +void
> +validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group)
> +{
> +  bool change_p = validate_change (object, loc, new_rtx, in_group);
> +  gcc_assert (change_p);
> +}
> +
> +/* Return true if it is NONVLMAX AVL TYPE.  */
> +bool
> +nonvlmax_avl_type_p (rtx_insn *rinsn)
> +{
> +  extract_insn_cached (rinsn);
> +  int index = get_attr_avl_type_idx (rinsn);
> +  if (index == INVALID_ATTRIBUTE)
> +    return false;
> +  rtx avl_type = recog_data.operand[index];
> +  return INTVAL (avl_type) == NONVLMAX;
> +}
> +
> +/* Return true if RTX is RVV VLMAX AVL.  */
> +bool
> +vlmax_avl_p (rtx x)
> +{
> +  return x && rtx_equal_p (x, RVV_VLMAX);
> +}
> +
> +/* Helper function to get SEW operand. We always have SEW value for
> +   all RVV instructions that have VTYPE OP.  */
> +uint8_t
> +get_sew (rtx_insn *rinsn)
> +{
> +  return get_attr_sew (rinsn);
> +}
> +
> +/* Helper function to get VLMUL operand. We always have VLMUL value for
> +   all RVV instructions that have VTYPE OP. */
> +enum vlmul_type
> +get_vlmul (rtx_insn *rinsn)
> +{
> +  return (enum vlmul_type) get_attr_vlmul (rinsn);
> +}
> +
> +/* Count the number of REGNO in RINSN.  */
> +int
> +count_regno_occurrences (rtx_insn *rinsn, unsigned int regno)
> +{
> +  int count = 0;
> +  extract_insn (rinsn);
> +  for (int i = 0; i < recog_data.n_operands; i++)
> +    if (refers_to_regno_p (regno, recog_data.operand[i]))
> +      count++;
> +  return count;
> +}
> +
>  } // namespace riscv_vector
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 73a6d4b7406..77dbf159d41 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -255,12 +255,6 @@ policy_to_str (bool agnostic_p)
>    return agnostic_p ? "agnostic" : "undisturbed";
>  }
>
> -static bool
> -vlmax_avl_p (rtx x)
> -{
> -  return x && rtx_equal_p (x, RVV_VLMAX);
> -}
> -
>  /* Return true if it is an RVV instruction depends on VTYPE global
>     status register.  */
>  static bool
> @@ -269,14 +263,6 @@ has_vtype_op (rtx_insn *rinsn)
>    return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn);
>  }
>
> -/* Return true if it is an RVV instruction depends on VL global
> -   status register.  */
> -static bool
> -has_vl_op (rtx_insn *rinsn)
> -{
> -  return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn);
> -}
> -
>  /* Return true if the instruction ignores VLMUL field of VTYPE.  */
>  static bool
>  ignore_vlmul_insn_p (rtx_insn *rinsn)
> @@ -371,32 +357,6 @@ get_avl (rtx_insn *rinsn)
>    return recog_data.operand[get_attr_vl_op_idx (rinsn)];
>  }
>
> -/* Helper function to get SEW operand. We always have SEW value for
> -   all RVV instructions that have VTYPE OP.  */
> -static uint8_t
> -get_sew (rtx_insn *rinsn)
> -{
> -  return get_attr_sew (rinsn);
> -}
> -
> -/* Helper function to get VLMUL operand. We always have VLMUL value for
> -   all RVV instructions that have VTYPE OP. */
> -static enum vlmul_type
> -get_vlmul (rtx_insn *rinsn)
> -{
> -  return (enum vlmul_type) get_attr_vlmul (rinsn);
> -}
> -
> -/* Get default tail policy.  */
> -static bool
> -get_default_ta ()
> -{
> -  /* For the instruction that doesn't require TA, we still need a default value
> -     to emit vsetvl. We pick up the default value according to prefer policy. */
> -  return (bool) (get_prefer_tail_policy () & 0x1
> -                || (get_prefer_tail_policy () >> 1 & 0x1));
> -}
> -
>  /* Get default mask policy.  */
>  static bool
>  get_default_ma ()
> @@ -407,16 +367,6 @@ get_default_ma ()
>                  || (get_prefer_mask_policy () >> 1 & 0x1));
>  }
>
> -/* Helper function to get TA operand.  */
> -static bool
> -tail_agnostic_p (rtx_insn *rinsn)
> -{
> -  /* If it doesn't have TA, we return agnostic by default.  */
> -  extract_insn_cached (rinsn);
> -  int ta = get_attr_ta (rinsn);
> -  return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta);
> -}
> -
>  /* Helper function to get MA operand.  */
>  static bool
>  mask_agnostic_p (rtx_insn *rinsn)
> @@ -476,18 +426,6 @@ get_max_float_sew ()
>    gcc_unreachable ();
>  }
>
> -/* Count the number of REGNO in RINSN.  */
> -static int
> -count_regno_occurrences (rtx_insn *rinsn, unsigned int regno)
> -{
> -  int count = 0;
> -  extract_insn (rinsn);
> -  for (int i = 0; i < recog_data.n_operands; i++)
> -    if (refers_to_regno_p (regno, recog_data.operand[i]))
> -      count++;
> -  return count;
> -}
> -
>  enum def_type
>  {
>    REAL_SET = 1 << 0,
> @@ -696,14 +634,6 @@ has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int regno)
>    return true;
>  }
>
> -/* Change insn and Assert the change always happens.  */
> -static void
> -validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group)
> -{
> -  bool change_p = validate_change (object, loc, new_rtx, in_group);
> -  gcc_assert (change_p);
> -}
> -
>  /* This flags indicates the minimum demand of the vl and vtype values by the
>     RVV instruction. For example, DEMAND_RATIO_P indicates that this RVV
>     instruction only needs the SEW/LMUL ratio to remain the same, and does not
> --
> 2.36.3
>

Thanks. Committed with NFC mentioned.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-10-25 17:06
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Export some functions from riscv-vsetvl to riscv-v
LGTM, but plz mention it's NFC in the title, no v2 needed :)
 
On Wed, Oct 25, 2023 at 5:03 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> Address kito's comments of AVL propagation patch.
>
> Export the functions that are not only used by VSETVL PASS but also AVL propagation PASS.
>
> No functionality change.
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl to riscv-v
>         (tail_agnostic_p): Ditto.
>         (validate_change_or_fail): Ditto.
>         (nonvlmax_avl_type_p): Ditto.
>         (vlmax_avl_p): Ditto.
>         (get_sew): Ditto.
>         (enum vlmul_type): Ditto.
>         (count_regno_occurrences): Ditto.
>         * config/riscv/riscv-v.cc (has_vl_op): Ditto.
>         (get_default_ta): Ditto.
>         (tail_agnostic_p): Ditto.
>         (validate_change_or_fail): Ditto.
>         (nonvlmax_avl_type_p): Ditto.
>         (vlmax_avl_p): Ditto.
>         (get_sew): Ditto.
>         (enum vlmul_type): Ditto.
>         (get_vlmul): Ditto.
>         (count_regno_occurrences): Ditto.
>         * config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto.
>         (has_vl_op): Ditto.
>         (get_sew): Ditto.
>         (get_vlmul): Ditto.
>         (get_default_ta): Ditto.
>         (tail_agnostic_p): Ditto.
>         (count_regno_occurrences): Ditto.
>         (validate_change_or_fail): Ditto.
>
> ---
>  gcc/config/riscv/riscv-protos.h  |  8 +++
>  gcc/config/riscv/riscv-v.cc      | 83 ++++++++++++++++++++++++++++++++
>  gcc/config/riscv/riscv-vsetvl.cc | 70 ---------------------------
>  3 files changed, 91 insertions(+), 70 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index fffd9cd0b8a..668d75043ca 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -560,6 +560,14 @@ bool cmp_lmul_gt_one (machine_mode);
>  bool gather_scatter_valid_offset_mode_p (machine_mode);
>  bool vls_mode_valid_p (machine_mode);
>  bool vlmax_avl_type_p (rtx_insn *);
> +bool has_vl_op (rtx_insn *);
> +bool tail_agnostic_p (rtx_insn *);
> +void validate_change_or_fail (rtx, rtx *, rtx, bool);
> +bool nonvlmax_avl_type_p (rtx_insn *);
> +bool vlmax_avl_p (rtx);
> +uint8_t get_sew (rtx_insn *);
> +enum vlmul_type get_vlmul (rtx_insn *);
> +int count_regno_occurrences (rtx_insn *, unsigned int);
>  }
>
>  /* We classify builtin types into two classes:
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index d439ec06af0..3fe8125801b 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4447,4 +4447,87 @@ vlmax_avl_type_p (rtx_insn *rinsn)
>    return INTVAL (avl_type) == VLMAX;
>  }
>
> +/* Return true if it is an RVV instruction depends on VL global
> +   status register.  */
> +bool
> +has_vl_op (rtx_insn *rinsn)
> +{
> +  return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn);
> +}
> +
> +/* Get default tail policy.  */
> +static bool
> +get_default_ta ()
> +{
> +  /* For the instruction that doesn't require TA, we still need a default value
> +     to emit vsetvl. We pick up the default value according to prefer policy. */
> +  return (bool) (get_prefer_tail_policy () & 0x1
> +                || (get_prefer_tail_policy () >> 1 & 0x1));
> +}
> +
> +/* Helper function to get TA operand.  */
> +bool
> +tail_agnostic_p (rtx_insn *rinsn)
> +{
> +  /* If it doesn't have TA, we return agnostic by default.  */
> +  extract_insn_cached (rinsn);
> +  int ta = get_attr_ta (rinsn);
> +  return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta);
> +}
> +
> +/* Change insn and Assert the change always happens.  */
> +void
> +validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group)
> +{
> +  bool change_p = validate_change (object, loc, new_rtx, in_group);
> +  gcc_assert (change_p);
> +}
> +
> +/* Return true if it is NONVLMAX AVL TYPE.  */
> +bool
> +nonvlmax_avl_type_p (rtx_insn *rinsn)
> +{
> +  extract_insn_cached (rinsn);
> +  int index = get_attr_avl_type_idx (rinsn);
> +  if (index == INVALID_ATTRIBUTE)
> +    return false;
> +  rtx avl_type = recog_data.operand[index];
> +  return INTVAL (avl_type) == NONVLMAX;
> +}
> +
> +/* Return true if RTX is RVV VLMAX AVL.  */
> +bool
> +vlmax_avl_p (rtx x)
> +{
> +  return x && rtx_equal_p (x, RVV_VLMAX);
> +}
> +
> +/* Helper function to get SEW operand. We always have SEW value for
> +   all RVV instructions that have VTYPE OP.  */
> +uint8_t
> +get_sew (rtx_insn *rinsn)
> +{
> +  return get_attr_sew (rinsn);
> +}
> +
> +/* Helper function to get VLMUL operand. We always have VLMUL value for
> +   all RVV instructions that have VTYPE OP. */
> +enum vlmul_type
> +get_vlmul (rtx_insn *rinsn)
> +{
> +  return (enum vlmul_type) get_attr_vlmul (rinsn);
> +}
> +
> +/* Count the number of REGNO in RINSN.  */
> +int
> +count_regno_occurrences (rtx_insn *rinsn, unsigned int regno)
> +{
> +  int count = 0;
> +  extract_insn (rinsn);
> +  for (int i = 0; i < recog_data.n_operands; i++)
> +    if (refers_to_regno_p (regno, recog_data.operand[i]))
> +      count++;
> +  return count;
> +}
> +
>  } // namespace riscv_vector
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 73a6d4b7406..77dbf159d41 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -255,12 +255,6 @@ policy_to_str (bool agnostic_p)
>    return agnostic_p ? "agnostic" : "undisturbed";
>  }
>
> -static bool
> -vlmax_avl_p (rtx x)
> -{
> -  return x && rtx_equal_p (x, RVV_VLMAX);
> -}
> -
>  /* Return true if it is an RVV instruction depends on VTYPE global
>     status register.  */
>  static bool
> @@ -269,14 +263,6 @@ has_vtype_op (rtx_insn *rinsn)
>    return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn);
>  }
>
> -/* Return true if it is an RVV instruction depends on VL global
> -   status register.  */
> -static bool
> -has_vl_op (rtx_insn *rinsn)
> -{
> -  return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn);
> -}
> -
>  /* Return true if the instruction ignores VLMUL field of VTYPE.  */
>  static bool
>  ignore_vlmul_insn_p (rtx_insn *rinsn)
> @@ -371,32 +357,6 @@ get_avl (rtx_insn *rinsn)
>    return recog_data.operand[get_attr_vl_op_idx (rinsn)];
>  }
>
> -/* Helper function to get SEW operand. We always have SEW value for
> -   all RVV instructions that have VTYPE OP.  */
> -static uint8_t
> -get_sew (rtx_insn *rinsn)
> -{
> -  return get_attr_sew (rinsn);
> -}
> -
> -/* Helper function to get VLMUL operand. We always have VLMUL value for
> -   all RVV instructions that have VTYPE OP. */
> -static enum vlmul_type
> -get_vlmul (rtx_insn *rinsn)
> -{
> -  return (enum vlmul_type) get_attr_vlmul (rinsn);
> -}
> -
> -/* Get default tail policy.  */
> -static bool
> -get_default_ta ()
> -{
> -  /* For the instruction that doesn't require TA, we still need a default value
> -     to emit vsetvl. We pick up the default value according to prefer policy. */
> -  return (bool) (get_prefer_tail_policy () & 0x1
> -                || (get_prefer_tail_policy () >> 1 & 0x1));
> -}
> -
>  /* Get default mask policy.  */
>  static bool
>  get_default_ma ()
> @@ -407,16 +367,6 @@ get_default_ma ()
>                  || (get_prefer_mask_policy () >> 1 & 0x1));
>  }
>
> -/* Helper function to get TA operand.  */
> -static bool
> -tail_agnostic_p (rtx_insn *rinsn)
> -{
> -  /* If it doesn't have TA, we return agnostic by default.  */
> -  extract_insn_cached (rinsn);
> -  int ta = get_attr_ta (rinsn);
> -  return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta);
> -}
> -
>  /* Helper function to get MA operand.  */
>  static bool
>  mask_agnostic_p (rtx_insn *rinsn)
> @@ -476,18 +426,6 @@ get_max_float_sew ()
>    gcc_unreachable ();
>  }
>
> -/* Count the number of REGNO in RINSN.  */
> -static int
> -count_regno_occurrences (rtx_insn *rinsn, unsigned int regno)
> -{
> -  int count = 0;
> -  extract_insn (rinsn);
> -  for (int i = 0; i < recog_data.n_operands; i++)
> -    if (refers_to_regno_p (regno, recog_data.operand[i]))
> -      count++;
> -  return count;
> -}
> -
>  enum def_type
>  {
>    REAL_SET = 1 << 0,
> @@ -696,14 +634,6 @@ has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int regno)
>    return true;
>  }
>
> -/* Change insn and Assert the change always happens.  */
> -static void
> -validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group)
> -{
> -  bool change_p = validate_change (object, loc, new_rtx, in_group);
> -  gcc_assert (change_p);
> -}
> -
>  /* This flags indicates the minimum demand of the vl and vtype values by the
>     RVV instruction. For example, DEMAND_RATIO_P indicates that this RVV
>     instruction only needs the SEW/LMUL ratio to remain the same, and does not
> --
> 2.36.3
>