From patchwork Mon Oct 23 09:46:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiahao Xu X-Patchwork-Id: 1853622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SDVjM2ZXJz23jV for ; Mon, 23 Oct 2023 20:47:35 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 645F2385840F for ; Mon, 23 Oct 2023 09:47:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 0FC253858C2A for ; Mon, 23 Oct 2023 09:47:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0FC253858C2A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0FC253858C2A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698054441; cv=none; b=DM8dkVt2biHLBSOAI3sPSdRnDx/nOJU8aEh+G/SAhSmkJqZal3g5kvc/8/I5di9sm37xUWiM4JlerVRO18VeRvLAnzEzCLJprJYBDXlMDk3DQ0ZLDDaOHh31cCrzOSlT7UTYwXB7nYNeJ2FOYGgfApdgWJN9Srz27laODwHXMWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698054441; c=relaxed/simple; bh=xaBUMJQWmN5Ggunb9D5+SB5lEFirbugm0bNcMJp1xOI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=gtH+6ADnTL2LC5gE6hUtjaXWYLaw9QQnsuZsDAHtGZLxMi1++Gu2+y/qHczg/wBWqZ8vhDZyk7FUOtWZezlw52tRSq0vLE8q0s6BZHxuFgT+osASgOU3YJT9eEzojElesNa2O2zUq6FXpwOVEDsi9wXL7FnSh3uEwlN9IU3VdcM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8CxfOoeQTZl7OszAA--.8096S3; Mon, 23 Oct 2023 17:47:10 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxL90dQTZlECwvAA--.36710S4; Mon, 23 Oct 2023 17:47:09 +0800 (CST) From: Jiahao Xu To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn, Jiahao Xu Subject: [PATCH] LoongArch:Enable vcond_mask_mn expanders for SF/DF modes. Date: Mon, 23 Oct 2023 17:46:29 +0800 Message-Id: <20231023094629.5189-1-xujiahao@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxL90dQTZlECwvAA--.36710S4 X-CM-SenderInfo: 50xmxthkdrqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj9fXoW3tw17XryDuw1DurW7CF45Jwc_yoW8XFy5Co Z5Ar93J345ursakrZrKr1xXrn7A34Iyrn8uayavFW5GanxX3s8C3y5tw4fZr48A3W8Zr18 A34xK3WkA3yqvrn8l-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYx7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Cr1j6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4IxYO2xFxVAFwI0_JF0_Jw1lx2IqxVAq x4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r 1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF 7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxV WUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UE -erUUUUU= X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org If the vcond_mask patterns don't support fp modes, the vector FP comparison instructions will not be generated. gcc/ChangeLog: * config/loongarch/lasx.md (vcond_mask_): Change to (vcond_mask_): this. * config/loongarch/lsx.md (vcond_mask_): Change to (vcond_mask_): this. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-cond-1.c: New test. * gcc.target/loongarch/vector/lasx/lasx-vcond-2.c: Ditto. * gcc.target/loongarch/vector/lsx/lsx-vcond-2.c: Ditto. * gcc.target/loongarch/vector/lsx/lsx-vcond-2.c: Ditto. Change-Id: If9716f356c0b83748a208235e835feb402b5c78f diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 442fda24606..ba2c5eec7d0 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -906,15 +906,15 @@ (define_expand "vcond" }) ;; Same as vcond_ -(define_expand "vcond_mask_" - [(match_operand:ILASX 0 "register_operand") - (match_operand:ILASX 1 "reg_or_m1_operand") - (match_operand:ILASX 2 "reg_or_0_operand") - (match_operand:ILASX 3 "register_operand")] +(define_expand "vcond_mask_" + [(match_operand:LASX 0 "register_operand") + (match_operand:LASX 1 "reg_or_m1_operand") + (match_operand:LASX 2 "reg_or_0_operand") + (match_operand: 3 "register_operand")] "ISA_HAS_LASX" { - loongarch_expand_vec_cond_mask_expr (mode, - mode, operands); + loongarch_expand_vec_cond_mask_expr (mode, + mode, operands); DONE; }) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index b4e92ae9c54..7e77ac4ad6a 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -644,15 +644,15 @@ (define_expand "vcond" DONE; }) -(define_expand "vcond_mask_" - [(match_operand:ILSX 0 "register_operand") - (match_operand:ILSX 1 "reg_or_m1_operand") - (match_operand:ILSX 2 "reg_or_0_operand") - (match_operand:ILSX 3 "register_operand")] +(define_expand "vcond_mask_" + [(match_operand:LSX 0 "register_operand") + (match_operand:LSX 1 "reg_or_m1_operand") + (match_operand:LSX 2 "reg_or_0_operand") + (match_operand: 3 "register_operand")] "ISA_HAS_LSX" { - loongarch_expand_vec_cond_mask_expr (mode, - mode, operands); + loongarch_expand_vec_cond_mask_expr (mode, + mode, operands); DONE; }) diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-1.c new file mode 100644 index 00000000000..ee9cb1a1fa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-unroll-loops -fno-vect-cost-model -mlasx" } */ + +#include + +#define DEF_VCOND_VAR(DATA_TYPE, CMP_TYPE, COND, SUFFIX) \ + void __attribute__ ((noinline, noclone)) \ + vcond_var_##CMP_TYPE##_##SUFFIX (DATA_TYPE *__restrict__ r, \ + DATA_TYPE *__restrict__ x, \ + DATA_TYPE *__restrict__ y, \ + CMP_TYPE *__restrict__ a, \ + CMP_TYPE *__restrict__ b, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + DATA_TYPE xval = x[i], yval = y[i]; \ + CMP_TYPE aval = a[i], bval = b[i]; \ + r[i] = aval COND bval ? xval : yval; \ + } \ + } + +#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX) \ + T (int8_t, int8_t, COND, SUFFIX) \ + T (int16_t, int16_t, COND, SUFFIX) \ + T (int32_t, int32_t, COND, SUFFIX) \ + T (int64_t, int64_t, COND, SUFFIX) \ + T (float, int32_t, COND, SUFFIX##_float) \ + T (double, int64_t, COND, SUFFIX##_double) + +#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX) \ + T (uint8_t, uint8_t, COND, SUFFIX) \ + T (uint16_t, uint16_t, COND, SUFFIX) \ + T (uint32_t, uint32_t, COND, SUFFIX) \ + T (uint64_t, uint64_t, COND, SUFFIX) \ + T (float, uint32_t, COND, SUFFIX##_float) \ + T (double, uint64_t, COND, SUFFIX##_double) + +#define TEST_COND_VAR_ALL(T, COND, SUFFIX) \ + TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX) \ + TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX) + +#define TEST_VAR_ALL(T) \ + TEST_COND_VAR_ALL (T, >, _gt) \ + TEST_COND_VAR_ALL (T, <, _lt) \ + TEST_COND_VAR_ALL (T, >=, _ge) \ + TEST_COND_VAR_ALL (T, <=, _le) \ + TEST_COND_VAR_ALL (T, ==, _eq) \ + TEST_COND_VAR_ALL (T, !=, _ne) + +TEST_VAR_ALL (DEF_VCOND_VAR) + +/* { dg-final { scan-assembler-times {\txvslt\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\txvslt\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\txvslt\.w} 4 } } */ +/* { dg-final { scan-assembler-times {\txvslt\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.w} 4 } } */ +/* { dg-final { scan-assembler-times {\txvsle\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.w} 4 } } */ +/* { dg-final { scan-assembler-times {\txvseq\.d} 4 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c new file mode 100644 index 00000000000..5f40ed44c2d --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vcond-2.c @@ -0,0 +1,87 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -mlasx" } */ + +#include + +#define eq(A, B) ((A) == (B)) +#define ne(A, B) ((A) != (B)) +#define olt(A, B) ((A) < (B)) +#define ole(A, B) ((A) <= (B)) +#define oge(A, B) ((A) >= (B)) +#define ogt(A, B) ((A) > (B)) +#define ordered(A, B) (!__builtin_isunordered (A, B)) +#define unordered(A, B) (__builtin_isunordered (A, B)) +#define ueq(A, B) (!__builtin_islessgreater (A, B)) +#define ult(A, B) (__builtin_isless (A, B)) +#define ule(A, B) (__builtin_islessequal (A, B)) +#define uge(A, B) (__builtin_isgreaterequal (A, B)) +#define ugt(A, B) (__builtin_isgreater (A, B)) +#define nueq(A, B) (__builtin_islessgreater (A, B)) +#define nult(A, B) (!__builtin_isless (A, B)) +#define nule(A, B) (!__builtin_islessequal (A, B)) +#define nuge(A, B) (!__builtin_isgreaterequal (A, B)) +#define nugt(A, B) (!__builtin_isgreater (A, B)) + +#define TEST_LOOP(TYPE1, TYPE2, CMP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE1##_##TYPE2##_##CMP##_var (TYPE1 *restrict dest, \ + TYPE1 *restrict src, \ + TYPE1 fallback, \ + TYPE2 *restrict a, \ + TYPE2 *restrict b, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + {\ + TYPE2 aval = a[i]; \ + TYPE2 bval = b[i]; \ + TYPE1 srcval = src[i]; \ + dest[i] = CMP (aval, bval) ? srcval : fallback; \ + }\ + } + +#define TEST_CMP(CMP) \ + TEST_LOOP (int32_t, float, CMP) \ + TEST_LOOP (uint32_t, float, CMP) \ + TEST_LOOP (float, float, CMP) \ + TEST_LOOP (int64_t, double, CMP) \ + TEST_LOOP (uint64_t, double, CMP) \ + TEST_LOOP (double, double, CMP) + +TEST_CMP (eq) +TEST_CMP (ne) +TEST_CMP (olt) +TEST_CMP (ole) +TEST_CMP (oge) +TEST_CMP (ogt) +TEST_CMP (ordered) +TEST_CMP (unordered) +TEST_CMP (ueq) +TEST_CMP (ult) +TEST_CMP (ule) +TEST_CMP (uge) +TEST_CMP (ugt) +TEST_CMP (nueq) +TEST_CMP (nult) +TEST_CMP (nule) +TEST_CMP (nuge) +TEST_CMP (nugt) + +/* { dg-final { scan-assembler-times {\txvfcmp\.ceq\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.ceq\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cne\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cne\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.slt\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.slt\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.sle\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.sle\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cor\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cor\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cun\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cun\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cueq\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cueq\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cule\.s} 8 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cule\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cult\.s} 8 } } */ +/* { dg-final { scan-assembler-times {\txvfcmp\.cult\.d} 8 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-1.c new file mode 100644 index 00000000000..138adccfaf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-unroll-loops -fno-vect-cost-model -mlsx" } */ + +#include + +#define DEF_VCOND_VAR(DATA_TYPE, CMP_TYPE, COND, SUFFIX) \ + void __attribute__ ((noinline, noclone)) \ + vcond_var_##CMP_TYPE##_##SUFFIX (DATA_TYPE *__restrict__ r, \ + DATA_TYPE *__restrict__ x, \ + DATA_TYPE *__restrict__ y, \ + CMP_TYPE *__restrict__ a, \ + CMP_TYPE *__restrict__ b, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + DATA_TYPE xval = x[i], yval = y[i]; \ + CMP_TYPE aval = a[i], bval = b[i]; \ + r[i] = aval COND bval ? xval : yval; \ + } \ + } + +#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX) \ + T (int8_t, int8_t, COND, SUFFIX) \ + T (int16_t, int16_t, COND, SUFFIX) \ + T (int32_t, int32_t, COND, SUFFIX) \ + T (int64_t, int64_t, COND, SUFFIX) \ + T (float, int32_t, COND, SUFFIX##_float) \ + T (double, int64_t, COND, SUFFIX##_double) + +#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX) \ + T (uint8_t, uint8_t, COND, SUFFIX) \ + T (uint16_t, uint16_t, COND, SUFFIX) \ + T (uint32_t, uint32_t, COND, SUFFIX) \ + T (uint64_t, uint64_t, COND, SUFFIX) \ + T (float, uint32_t, COND, SUFFIX##_float) \ + T (double, uint64_t, COND, SUFFIX##_double) + +#define TEST_COND_VAR_ALL(T, COND, SUFFIX) \ + TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX) \ + TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX) + +#define TEST_VAR_ALL(T) \ + TEST_COND_VAR_ALL (T, >, _gt) \ + TEST_COND_VAR_ALL (T, <, _lt) \ + TEST_COND_VAR_ALL (T, >=, _ge) \ + TEST_COND_VAR_ALL (T, <=, _le) \ + TEST_COND_VAR_ALL (T, ==, _eq) \ + TEST_COND_VAR_ALL (T, !=, _ne) + +TEST_VAR_ALL (DEF_VCOND_VAR) + +/* { dg-final { scan-assembler-times {\tvslt\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\tvslt\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\tvslt\.w} 4 } } */ +/* { dg-final { scan-assembler-times {\tvslt\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsle\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsle\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsle\.w} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsle\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tvseq\.b} 4 } } */ +/* { dg-final { scan-assembler-times {\tvseq\.h} 4 } } */ +/* { dg-final { scan-assembler-times {\tvseq\.w} 4 } } */ +/* { dg-final { scan-assembler-times {\tvseq\.d} 4 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c new file mode 100644 index 00000000000..e8fe31f8ff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vcond-2.c @@ -0,0 +1,87 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -mlsx" } */ + +#include + +#define eq(A, B) ((A) == (B)) +#define ne(A, B) ((A) != (B)) +#define olt(A, B) ((A) < (B)) +#define ole(A, B) ((A) <= (B)) +#define oge(A, B) ((A) >= (B)) +#define ogt(A, B) ((A) > (B)) +#define ordered(A, B) (!__builtin_isunordered (A, B)) +#define unordered(A, B) (__builtin_isunordered (A, B)) +#define ueq(A, B) (!__builtin_islessgreater (A, B)) +#define ult(A, B) (__builtin_isless (A, B)) +#define ule(A, B) (__builtin_islessequal (A, B)) +#define uge(A, B) (__builtin_isgreaterequal (A, B)) +#define ugt(A, B) (__builtin_isgreater (A, B)) +#define nueq(A, B) (__builtin_islessgreater (A, B)) +#define nult(A, B) (!__builtin_isless (A, B)) +#define nule(A, B) (!__builtin_islessequal (A, B)) +#define nuge(A, B) (!__builtin_isgreaterequal (A, B)) +#define nugt(A, B) (!__builtin_isgreater (A, B)) + +#define TEST_LOOP(TYPE1, TYPE2, CMP) \ + void __attribute__ ((noinline, noclone)) \ + test_##TYPE1##_##TYPE2##_##CMP##_var (TYPE1 *restrict dest, \ + TYPE1 *restrict src, \ + TYPE1 fallback, \ + TYPE2 *restrict a, \ + TYPE2 *restrict b, \ + int count) \ + { \ + for (int i = 0; i < count; ++i) \ + {\ + TYPE2 aval = a[i]; \ + TYPE2 bval = b[i]; \ + TYPE1 srcval = src[i]; \ + dest[i] = CMP (aval, bval) ? srcval : fallback; \ + }\ + } + +#define TEST_CMP(CMP) \ + TEST_LOOP (int32_t, float, CMP) \ + TEST_LOOP (uint32_t, float, CMP) \ + TEST_LOOP (float, float, CMP) \ + TEST_LOOP (int64_t, double, CMP) \ + TEST_LOOP (uint64_t, double, CMP) \ + TEST_LOOP (double, double, CMP) + +TEST_CMP (eq) +TEST_CMP (ne) +TEST_CMP (olt) +TEST_CMP (ole) +TEST_CMP (oge) +TEST_CMP (ogt) +TEST_CMP (ordered) +TEST_CMP (unordered) +TEST_CMP (ueq) +TEST_CMP (ult) +TEST_CMP (ule) +TEST_CMP (uge) +TEST_CMP (ugt) +TEST_CMP (nueq) +TEST_CMP (nult) +TEST_CMP (nule) +TEST_CMP (nuge) +TEST_CMP (nugt) + +/* { dg-final { scan-assembler-times {\tvfcmp\.ceq\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.ceq\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cne\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cne\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.slt\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.slt\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.sle\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.sle\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cor\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cor\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cun\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cun\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cueq\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cueq\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cule\.s} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cule\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cult\.s} 8 } } */ +/* { dg-final { scan-assembler-times {\tvfcmp\.cult\.d} 8 } } */