From patchwork Fri Oct 13 07:20:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1847884 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=IlF6h4Ma; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4S6Hx24Zg2z1yqj for ; Fri, 13 Oct 2023 18:21:10 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C9323858039 for ; Fri, 13 Oct 2023 07:21:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 8A0C03858D1E for ; Fri, 13 Oct 2023 07:20:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A0C03858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697181646; x=1728717646; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=yIMyXLNhTs+ekEWCn6G6elpUBKdO4HQeDzV7iUqgdkM=; b=IlF6h4MaVrTcSc3zWSIBGhVEghRRF8OHs28keQ9hy4t1N4mm7YOPamX6 XmvAeo3IZ2c/CJoKPo8wSoGknbKSPcdouYBn3TKJ33OXfmnW9U7GC4DCK SX+eA0zJQVLyAcAyEkqkKOhu6UbXsh7qmbdho1k0s2QeWCdolhbP1Oo4A JY3LcupVcWl2vq4+4gAy5pHS5QRNVP1hXXZ7V84F/yeYGfT2wtuXglgZy lomJ3qep8S51yz4Qy/JI6e/fKSpcoeWfTHyDrYJIolphB8Acj3Mij4Ptz aU679AlLg73ClVbO5Q2n+9J+ulDJw5CrLmi5b0T7WxswRhvjrsrvewIkx w==; X-IronPort-AV: E=McAfee;i="6600,9927,10861"; a="388985024" X-IronPort-AV: E=Sophos;i="6.03,221,1694761200"; d="scan'208";a="388985024" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2023 00:20:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10861"; a="784042037" X-IronPort-AV: E=Sophos;i="6.03,221,1694761200"; d="scan'208";a="784042037" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga008.jf.intel.com with ESMTP; 13 Oct 2023 00:20:29 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 47EA810056F5; Fri, 13 Oct 2023 15:20:28 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Add test for FP llceil auto vectorization Date: Fri, 13 Oct 2023 15:20:27 +0800 Message-Id: <20231013072027.1687701-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li The below FP API are supported already by sharing the same standard name, as well as the machine mode. long long llceil (double); This patch would like to add the test cases for ensuring the correctness. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-llceil-run-0.c: New test. * gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- .../riscv/rvv/autovec/unop/math-llceil-0.c | 20 ++++++ .../rvv/autovec/unop/math-llceil-run-0.c | 64 +++++++++++++++++++ .../riscv/rvv/autovec/vls/math-llceil-0.c | 30 +++++++++ 3 files changed, 114 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-run-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c new file mode 100644 index 00000000000..3480c3ea91d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include +#include "test-math.h" + +/* +** test_double_int64_t___builtin_llceil: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ret +*/ +TEST_UNARY_CALL_CVT (double, int64_t, __builtin_llceil) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-run-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-run-0.c new file mode 100644 index 00000000000..5ccbe64ffb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-run-0.c @@ -0,0 +1,64 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +int64_t out[ARRAY_SIZE]; +int64_t ref[ARRAY_SIZE]; + +TEST_UNARY_CALL_CVT (double, int64_t, __builtin_llceil) +TEST_ASSERT (int64_t) + +TEST_INIT_CVT (double, 1.2, int64_t, __builtin_llceil (1.2), 1) +TEST_INIT_CVT (double, -1.2, int64_t, __builtin_llceil (-1.2), 2) +TEST_INIT_CVT (double, 0.5, int64_t, __builtin_llceil (0.5), 3) +TEST_INIT_CVT (double, -0.5, int64_t, __builtin_llceil (-0.5), 4) +TEST_INIT_CVT (double, 0.1, int64_t, __builtin_llceil (0.1), 5) +TEST_INIT_CVT (double, -0.1, int64_t, __builtin_llceil (-0.1), 6) +TEST_INIT_CVT (double, 3.0, int64_t, __builtin_llceil (3.0), 7) +TEST_INIT_CVT (double, -3.0, int64_t, __builtin_llceil (-3.0), 8) +TEST_INIT_CVT (double, 4503599627370495.5, int64_t, __builtin_llceil (4503599627370495.5), 9) +TEST_INIT_CVT (double, 4503599627370497.0, int64_t, __builtin_llceil (4503599627370497.0), 10) +TEST_INIT_CVT (double, -4503599627370495.5, int64_t, __builtin_llceil (-4503599627370495.5), 11) +TEST_INIT_CVT (double, -4503599627370496.0, int64_t, __builtin_llceil (-4503599627370496.0), 12) +TEST_INIT_CVT (double, 0.0, int64_t, __builtin_llceil (-0.0), 13) +TEST_INIT_CVT (double, -0.0, int64_t, __builtin_llceil (-0.0), 14) +TEST_INIT_CVT (double, 9223372036854774784.0, int64_t, __builtin_llceil (9223372036854774784.0), 15) +TEST_INIT_CVT (double, 9223372036854775808.0, int64_t, 0x7fffffffffffffff, 16) +TEST_INIT_CVT (double, -9223372036854775808.0, int64_t, __builtin_llceil (-9223372036854775808.0), 17) +TEST_INIT_CVT (double, -9223372036854777856.0, int64_t, 0x8000000000000000, 18) +TEST_INIT_CVT (double, __builtin_inf (), int64_t, __builtin_llceil (__builtin_inf ()), 19) +TEST_INIT_CVT (double, -__builtin_inf (), int64_t, __builtin_llceil (-__builtin_inf ()), 20) +TEST_INIT_CVT (double, __builtin_nan (""), int64_t, 0x7fffffffffffffff, 21) + +int +main () +{ + RUN_TEST_CVT (double, int64_t, 1, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 2, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 3, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 4, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 5, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 6, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 7, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 8, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 9, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 10, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 11, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 12, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 13, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 14, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 15, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 16, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 17, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 18, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 19, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 20, __builtin_llceil, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (double, int64_t, 21, __builtin_llceil, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c new file mode 100644 index 00000000000..204e3adefca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V_CVT (llceil, 1, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 2, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 4, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 8, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 16, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 32, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 64, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 128, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 256, double, int64_t, __builtin_llceil) +DEF_OP_V_CVT (llceil, 512, double, int64_t, __builtin_llceil) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 9 } } */