From patchwork Wed Sep 27 03:28:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1839996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=kwNX9K6G; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RwMXg1L5Lz1yp8 for ; Wed, 27 Sep 2023 13:29:06 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 76593385CCAC for ; Wed, 27 Sep 2023 03:29:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 6C2313858C74 for ; Wed, 27 Sep 2023 03:28:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6C2313858C74 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695785329; x=1727321329; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cXWdyXh4CcUmsarF+QWX55JVTauBhwYHUqMIX1pSJss=; b=kwNX9K6GCAXnx4xBmUIEGtaJnHKmyLA1WC3tsW94NqKYWDFvt66sfra1 Q4rB6NhOq6B9EyeB9mOEuDq6P0a8I6ZqBfn3Tbur9Vz+YS4OaBkVh1lIT Sv4wSU30idDMfVpKGZZHJPRkY3kVpktTJ0bBQFYmNxYkZjfPE7Tm5TxYr eczD97Ywcbhoe7ij8cgsttKuAdSuH60gW20767YJQU4wOmFSYv8bRaqnv 6DW3kbsU4mWbYJvQp9cSDAGESA7xu5P2RRHWo7zOBJYCxkLcFj9GKo6y7 H90rzre7uCzdJ9UVoF0CMBd5Tq1+0T4rqffM9xs+w/OVr5wh4Q3iqA80b Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10845"; a="361973550" X-IronPort-AV: E=Sophos;i="6.03,179,1694761200"; d="scan'208";a="361973550" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 20:28:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10845"; a="892436871" X-IronPort-AV: E=Sophos;i="6.03,179,1694761200"; d="scan'208";a="892436871" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 26 Sep 2023 20:27:26 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9EF1910056F8; Wed, 27 Sep 2023 11:28:31 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support FP trunc auto-vectorization Date: Wed, 27 Sep 2023 11:28:30 +0800 Message-Id: <20230927032830.2458012-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to support auto-vectorization for the trunc API in math.h. It depends on the -ffast-math option. When we would like to call trunc/truncf like v2 = trunc (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.rtz.x.f v3, v1 * vfcvt.f.x v2, v3 However, the floating point value may not need the cvt as above if its mantissa is zero. Take single precision floating point as example: +------------+---------------+-----------------+ | raw float | binary layout | after trunc | +------------+---------------+-----------------+ | -8388607.5 | 0xcaffffff | -8388607.0 | | 8388607.5 | 0x4affffff | 8388607.0 | | 8388608.0 | 0x4b000000 | 8388608.0 | | 8388609.0 | 0x4b000001 | 8388609.0 | +------------+---------------+-----------------+ All single floating point >= 8388608.0 will have all zero mantisaa. We leverage vmflt and mask to filter them out in vector and only do the cvt on mask. Befor this patch: math-trunc-1.c:21:1: missed: couldn't vectorize loop ... .L3: flw fa0,0(s0) addi s0,s0,4 addi s1,s1,4 call trunc fsw fa0,-4(s1) bne s0,s2,.L3 After this patch: vfabs.v v2,v1 vmflt.vf v0,v2,fa5 vfcvt.rtz.x.f.v v4,v1,v0.t vfcvt.f.x.v v2,v4,v0.t vfsgnj.vv v2,v2,v1 bne .L4 Please note VLS mode is also involved in this patch and covered by the test cases. gcc/ChangeLog: * config/riscv/autovec.md (btrunc2): New pattern. * config/riscv/riscv-protos.h (expand_vec_trunc): New func decl. * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): New func impl. (expand_vec_trunc): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/autovec.md | 10 ++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 32 +++++++++++ .../riscv/rvv/autovec/unop/math-trunc-0.c | 18 ++++++ .../riscv/rvv/autovec/unop/math-trunc-1.c | 18 ++++++ .../riscv/rvv/autovec/unop/math-trunc-2.c | 18 ++++++ .../riscv/rvv/autovec/unop/math-trunc-3.c | 20 +++++++ .../riscv/rvv/autovec/unop/math-trunc-run-1.c | 39 +++++++++++++ .../riscv/rvv/autovec/unop/math-trunc-run-2.c | 39 +++++++++++++ .../riscv/rvv/autovec/vls/math-trunc-1.c | 56 +++++++++++++++++++ 10 files changed, 251 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 798cf1272c5..680a3374972 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2261,3 +2261,13 @@ (define_expand "round2" DONE; } ) + +(define_expand "btrunc2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_trunc (operands[0], operands[1], mode, mode); + DONE; + } +) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 70ca244c591..536e70bdcd3 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -468,6 +468,7 @@ void expand_vec_floor (rtx, rtx, machine_mode, machine_mode); void expand_vec_nearbyint (rtx, rtx, machine_mode, machine_mode); void expand_vec_rint (rtx, rtx, machine_mode, machine_mode); void expand_vec_round (rtx, rtx, machine_mode, machine_mode); +void expand_vec_trunc (rtx, rtx, machine_mode, machine_mode); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, bool, void (*)(rtx *, rtx)); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5f738634219..8992977a51d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3624,6 +3624,16 @@ emit_vec_cvt_f_x (rtx op_dest, rtx op_src, rtx mask, emit_vlmax_insn (icode, type, cvt_fp_ops); } +static void +emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask, + machine_mode vec_mode) +{ + rtx cvt_x_ops[] = {op_dest, mask, op_dest, op_src}; + insn_code icode = code_for_pred (FIX, vec_mode); + + emit_vlmax_insn (icode, UNARY_OP_TAMU, cvt_x_ops); +} + void expand_vec_ceil (rtx op_0, rtx op_1, machine_mode vec_fp_mode, machine_mode vec_int_mode) @@ -3744,4 +3754,26 @@ expand_vec_round (rtx op_0, rtx op_1, machine_mode vec_fp_mode, emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); } +void +expand_vec_trunc (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, rounding to zero (aka truncate). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the rint result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + } // namespace riscv_vector diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c new file mode 100644 index 00000000000..e3046341b99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_truncf16: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_truncf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c new file mode 100644 index 00000000000..8100419d22f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_truncf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_truncf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c new file mode 100644 index 00000000000..40551f559a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_trunc: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_trunc) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c new file mode 100644 index 00000000000..bb113fd4f2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_truncf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_truncf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c new file mode 100644 index 00000000000..10faf4b0377 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_truncf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388607.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + RUN_TEST (float, 1, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_truncf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_truncf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c new file mode 100644 index 00000000000..62ac50cdfd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-run-2.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_trunc) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.2, -1.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370495.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370495.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + RUN_TEST (double, 1, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_trunc, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_trunc, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c new file mode 100644 index 00000000000..51211bd653e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (truncf16, 1, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 2, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 4, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 8, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 16, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 32, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 64, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 128, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 256, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 512, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 1024, _Float16, __builtin_truncf16) +DEF_OP_V (truncf16, 2048, _Float16, __builtin_truncf16) + +DEF_OP_V (truncf, 1, float, __builtin_truncf) +DEF_OP_V (truncf, 2, float, __builtin_truncf) +DEF_OP_V (truncf, 4, float, __builtin_truncf) +DEF_OP_V (truncf, 8, float, __builtin_truncf) +DEF_OP_V (truncf, 16, float, __builtin_truncf) +DEF_OP_V (truncf, 32, float, __builtin_truncf) +DEF_OP_V (truncf, 64, float, __builtin_truncf) +DEF_OP_V (truncf, 128, float, __builtin_truncf) +DEF_OP_V (truncf, 256, float, __builtin_truncf) +DEF_OP_V (truncf, 512, float, __builtin_truncf) +DEF_OP_V (truncf, 1024, float, __builtin_truncf) + +DEF_OP_V (trunc, 1, double, __builtin_trunc) +DEF_OP_V (trunc, 2, double, __builtin_trunc) +DEF_OP_V (trunc, 4, double, __builtin_trunc) +DEF_OP_V (trunc, 8, double, __builtin_trunc) +DEF_OP_V (trunc, 16, double, __builtin_trunc) +DEF_OP_V (trunc, 32, double, __builtin_trunc) +DEF_OP_V (trunc, 64, double, __builtin_trunc) +DEF_OP_V (trunc, 128, double, __builtin_trunc) +DEF_OP_V (trunc, 256, double, __builtin_trunc) +DEF_OP_V (trunc, 512, double, __builtin_trunc) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */