From patchwork Fri Sep 22 10:56:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 1838205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=nke6Pn0B; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RsTlH0nNpz1ynH for ; Fri, 22 Sep 2023 20:58:19 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 47FC938207E8 for ; Fri, 22 Sep 2023 10:58:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 923C8385414F for ; Fri, 22 Sep 2023 10:56:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 923C8385414F Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695380217; x=1726916217; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gbjJZ5mQzXr58cy8X9OzJNre4ls8Y6Q63SDE49DrNto=; b=nke6Pn0BszR83saZE0ziXQN4MlT+9qb/yjY9/Nwhjh8lNn6DVgyoc30W aZNTFYlS7j2KRAzIxM4lzyzRhVv421RWFQlmG7wOiLIMErv13RJmrTBDK B1arXnTQCpUbIef1aU+1CIt3k7gN/6hJCB37Cy3GssWKR3eZ2AsoVeS9x wHpslFly6SXtUpo6oU5FEkaHRH0qo0yEaH9S4RGfkk0KsyHjYUgI733z4 bG/6UkVnT4uhickVu4JIb2XsTg6Oo8Xkx9Q673fUqvqZAktx95mIjhWmB KuKZVfJurX2uRucuQMwa/+XpqviaigFjVsQPdN87+dwtF9c+kfC4W6gyC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="379680867" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="379680867" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 03:56:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="782615996" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="782615996" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2023 03:56:37 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C226410050EB; Fri, 22 Sep 2023 18:56:31 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, vmakarov@redhat.com, jakub@redhat.com, Kong Lingling , Hongtao Liu Subject: [PATCH 12/13] [APX_EGPR] Handle legacy insns that only support GPR16 (4/5) Date: Fri, 22 Sep 2023 18:56:30 +0800 Message-Id: <20230922105631.2298849-13-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230922105631.2298849-1-hongyu.wang@intel.com> References: <20230922105631.2298849-1-hongyu.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Kong Lingling The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns with evex counterpart, we assume auto promotion to EGPR under APX_F if the insn uses GPR32. So for below insns, we disabled EGPR usage for their sse mnenomics, while allowing egpr generation of their v prefixed mnemonics. insn list: 1. pabsb/pabsw/pabsd 2. pextrb/pextrw/pextrd/pextrq 3. pinsrb/pinsrd/pinsrq 4. pshufb 5. extractps/insertps 6. pmaddubsw 7. pmulhrsw 8. packusdw 9. palignr 10. movntdqa 11. mpsadbw 12. pmuldq/pmulld 13. pmaxsb/pmaxsd, pminsb/pminsd pmaxud/pmaxuw, pminud/pminuw 14. (pmovsxbw/pmovsxbd/pmovsxbq, pmovsxwd/pmovsxwq, pmovsxdq pmovzxbw/pmovzxbd/pmovzxbq, pmovzxwd/pmovzxwq, pmovzxdq) 15. aesdec/aesdeclast, aesenc/aesenclast 16. pclmulqdq 17. gf2p8affineqb/gf2p8affineinvqb/gf2p8mulb gcc/ChangeLog: * config/i386/i386.md (*movhi_internal): Split out non-gpr supported pextrw with mem constraint to avx/noavx alternatives, set jm and attr gpr32 0 to the noavx alternative. (*mov_internal): Likewise. * config/i386/mmx.md (mmx_pshufbv8qi3): Change "r/m/Bm" to "jr/jm/ja" and set_attr gpr32 0 for noavx alternative. (mmx_pshufbv4qi3): Likewise. (*mmx_pinsrd): Likewise. (*mmx_pinsrb): Likewise. (*pinsrb): Likewise. (mmx_pshufbv8qi3): Likewise. (mmx_pshufbv4qi3): Likewise. (@sse4_1_insertps_): Likewise. (*mmx_pextrw): Split altrenatives and map non-EGPR constraints, attr_gpr32 and attr_isa to noavx mnemonics. (*movv2qi_internal): Likewise. (*pextrw): Likewise. (*mmx_pextrb): Likewise. (*mmx_pextrb_zext): Likewise. (*pextrb): Likewise. (*pextrb_zext): Likewise. (vec_extractv2si_1): Likewise. (vec_extractv2si_1_zext): Likewise. * config/i386/sse.md: (vi128_h_r): New mode attr for pinsr{bw}/pextr{bw} with reg operand. (*abs2): Split altrenatives and %v in mnemonics, map non-EGPR constraints, gpr32 and isa attrs to noavx mnemonics. (*vec_extract): Likewise. (*vec_extract): Likewise for HFBF pattern. (*vec_extract_zext): Likewise. (*vec_extractv4si_1): Likewise. (*vec_extractv4si_zext): Likewise. (*vec_extractv2di_1): Likewise. (*vec_concatv2si_sse4_1): Likewise. (_pinsr): Likewise. (vec_concatv2di): Likewise. (*sse4_1_v2qiv2di2_1): Likewise. (ssse3_avx2>_pshufb3): Change "r/m/Bm" to "jr/jm/ja" and set_attr gpr32 0 for noavx alternative, split %v for avx/noavx alternatives if necessary. (*vec_concatv2sf_sse4_1): Likewise. (*sse4_1_extractps): Likewise. (vec_set_0): Likewise for VI4F_128. (*vec_setv4sf_sse4_1): Likewise. (@sse4_1_insertps): Likewise. (ssse3_pmaddubsw128): Likewise. (*_pmulhrsw3): Likewise. (_packusdw): Likewise. (_palignr): Likewise. (_movntdqa): Likewise. (_mpsadbw): Likewise. (*sse4_1_mulv2siv2di3): Likewise. (*_mul3): Likewise. (*sse4_1_3): Likewise. (*v8hi3): Likewise. (*v16qi3): Likewise. (*sse4_1_v8qiv8hi2_1): Likewise. (*sse4_1_zero_extendv8qiv8hi2_3): Likewise. (*sse4_1_zero_extendv8qiv8hi2_4): Likewise. (*sse4_1_v4qiv4si2_1): Likewise. (*sse4_1_v4hiv4si2_1): Likewise. (*sse4_1_zero_extendv4hiv4si2_3): Likewise. (*sse4_1_zero_extendv4hiv4si2_4): Likewise. (*sse4_1_v2hiv2di2_1): Likewise. (*sse4_1_v2siv2di2_1): Likewise. (*sse4_1_zero_extendv2siv2di2_3): Likewise. (*sse4_1_zero_extendv2siv2di2_4): Likewise. (aesdec): Likewise. (aesdeclast): Likewise. (aesenc): Likewise. (aesenclast): Likewise. (pclmulqdq): Likewise. (vgf2p8affineinvqb_): Likewise. (vgf2p8affineqb_): Likewise. (vgf2p8mulb_): Likewise. Co-authored-by: Hongyu Wang Co-authored-by: Hongtao Liu --- gcc/config/i386/i386.md | 42 +++--- gcc/config/i386/mmx.md | 143 ++++++++++++--------- gcc/config/i386/sse.md | 274 ++++++++++++++++++++++++++-------------- 3 files changed, 289 insertions(+), 170 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 271d417146c..c09ee3989cb 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2868,9 +2868,9 @@ (define_peephole2 (define_insn "*movhi_internal" [(set (match_operand:HI 0 "nonimmediate_operand" - "=r,r,r,m ,*k,*k ,r ,m ,*k ,?r,?*v,*v,*v,*v,m") + "=r,r,r,m ,*k,*k ,r ,m ,*k ,?r,?*v,*v,*v,*v,jm,m") (match_operand:HI 1 "general_operand" - "r ,n,m,rn,r ,*km,*k,*k,CBC,*v,r ,C ,*v,m ,*v"))] + "r ,n,m,rn,r ,*km,*k,*k,CBC,*v,r ,C ,*v,m ,*x,*v"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && ix86_hardreg_mov_ok (operands[0], operands[1])" { @@ -2925,15 +2925,21 @@ (define_insn "*movhi_internal" (cond [(eq_attr "alternative" "9,10,11,12,13") (const_string "sse2") (eq_attr "alternative" "14") - (const_string "sse4") + (const_string "sse4_noavx") + (eq_attr "alternative" "15") + (const_string "avx") ] (const_string "*"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "14") + (const_string "0") + (const_string "1"))) (set (attr "type") (cond [(eq_attr "alternative" "4,5,6,7") (const_string "mskmov") (eq_attr "alternative" "8") (const_string "msklog") - (eq_attr "alternative" "13,14") + (eq_attr "alternative" "13,14,15") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "ssemov") (const_string "sselog1")) @@ -2958,7 +2964,7 @@ (define_insn "*movhi_internal" (set (attr "prefix") (cond [(eq_attr "alternative" "4,5,6,7,8") (const_string "vex") - (eq_attr "alternative" "9,10,11,12,13,14") + (eq_attr "alternative" "9,10,11,12,13,14,15") (const_string "maybe_evex") ] (const_string "orig"))) @@ -2967,7 +2973,7 @@ (define_insn "*movhi_internal" (if_then_else (match_test "TARGET_AVX512FP16") (const_string "HI") (const_string "SI")) - (eq_attr "alternative" "13,14") + (eq_attr "alternative" "13,14,15") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "HI") (const_string "TI")) @@ -4320,9 +4326,9 @@ (define_mode_attr hfbfconstf (define_insn "*mov_internal" [(set (match_operand:HFBF 0 "nonimmediate_operand" - "=?r,?r,?r,?m,v,v,?r,m,?v,v") + "=?r,?r,?r,?m,v,v,?r,jm,m,?v,v") (match_operand:HFBF 1 "general_operand" - "r ,F ,m ,r,C,v, v,v,r ,m"))] + "r ,F ,m ,r,C,v, v,v,v,r ,m"))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && (lra_in_progress || reload_completed @@ -4358,18 +4364,24 @@ (define_insn "*mov_internal" } } [(set (attr "isa") - (cond [(eq_attr "alternative" "4,5,6,8,9") + (cond [(eq_attr "alternative" "4,5,6,9,10") (const_string "sse2") (eq_attr "alternative" "7") - (const_string "sse4") + (const_string "sse4_noavx") + (eq_attr "alternative" "8") + (const_string "avx") ] (const_string "*"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "8") + (const_string "0") + (const_string "1"))) (set (attr "type") (cond [(eq_attr "alternative" "4") (const_string "sselog1") - (eq_attr "alternative" "5,6,8") + (eq_attr "alternative" "5,6,9") (const_string "ssemov") - (eq_attr "alternative" "7,9") + (eq_attr "alternative" "7,8,10") (if_then_else (match_test ("TARGET_AVX512FP16")) (const_string "ssemov") @@ -4389,19 +4401,19 @@ (define_insn "*mov_internal" ] (const_string "imov"))) (set (attr "prefix") - (cond [(eq_attr "alternative" "4,5,6,7,8,9") + (cond [(eq_attr "alternative" "4,5,6,7,8,9,10") (const_string "maybe_vex") ] (const_string "orig"))) (set (attr "mode") (cond [(eq_attr "alternative" "4") (const_string "V4SF") - (eq_attr "alternative" "6,8") + (eq_attr "alternative" "6,9") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "HI") (const_string "SI")) - (eq_attr "alternative" "7,9") + (eq_attr "alternative" "7,8,10") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "HI") diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index ef578222945..73809585a5d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -418,9 +418,9 @@ (define_expand "movv2qi" (define_insn "*movv2qi_internal" [(set (match_operand:V2QI 0 "nonimmediate_operand" - "=r,r,r,m ,v,v,v,m,r,v") + "=r,r,r,m ,v,v,v,jm,m,r,v") (match_operand:V2QI 1 "general_operand" - "r ,C,m,rC,C,v,m,v,v,r"))] + "r ,C,m,rC,C,v,m,x,v,v,r"))] "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) @@ -453,20 +453,26 @@ (define_insn "*movv2qi_internal" } } [(set (attr "isa") - (cond [(eq_attr "alternative" "6,8,9") + (cond [(eq_attr "alternative" "6,9,10") (const_string "sse2") (eq_attr "alternative" "7") - (const_string "sse4") + (const_string "sse4_noavx") + (eq_attr "alternative" "8") + (const_string "avx") ] (const_string "*"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "7") + (const_string "0") + (const_string "1"))) (set (attr "type") - (cond [(eq_attr "alternative" "6,7") + (cond [(eq_attr "alternative" "6,7,8") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "ssemov") (const_string "sselog1")) (eq_attr "alternative" "4") (const_string "sselog1") - (eq_attr "alternative" "5,8,9") + (eq_attr "alternative" "5,9,10") (const_string "ssemov") (match_test "optimize_function_for_size_p (cfun)") (const_string "imov") @@ -483,16 +489,16 @@ (define_insn "*movv2qi_internal" ] (const_string "imov"))) (set (attr "prefix") - (cond [(eq_attr "alternative" "4,5,6,7,8,9") + (cond [(eq_attr "alternative" "4,5,6,7,8,9,10") (const_string "maybe_evex") ] (const_string "orig"))) (set (attr "mode") - (cond [(eq_attr "alternative" "6,7") + (cond [(eq_attr "alternative" "6,7,8") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "HI") (const_string "TI")) - (eq_attr "alternative" "8,9") + (eq_attr "alternative" "9,10") (if_then_else (match_test "TARGET_AVX512FP16") (const_string "HI") (const_string "SI")) @@ -526,9 +532,9 @@ (define_insn "*movv2qi_internal" ] (const_string "HI"))) (set (attr "preferred_for_speed") - (cond [(eq_attr "alternative" "8") + (cond [(eq_attr "alternative" "9") (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC") - (eq_attr "alternative" "9") + (eq_attr "alternative" "10") (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC") ] (symbol_ref "true")))]) @@ -1167,7 +1173,7 @@ (define_expand "vcondv2sf" (define_insn "@sse4_1_insertps_" [(set (match_operand:V2FI 0 "register_operand" "=Yr,*x,v") (unspec:V2FI - [(match_operand:V2FI 2 "nonimmediate_operand" "Yrm,*xm,vm") + [(match_operand:V2FI 2 "nonimmediate_operand" "Yrjm,*xjm,vm") (match_operand:V2FI 1 "register_operand" "0,0,v") (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_INSERTPS))] @@ -1193,6 +1199,7 @@ (define_insn "@sse4_1_insertps_" } } [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,1,*") (set_attr "prefix_extra" "1") @@ -3952,7 +3959,7 @@ (define_insn "*mmx_pinsrd" [(set (match_operand:V2SI 0 "register_operand" "=x,Yv") (vec_merge:V2SI (vec_duplicate:V2SI - (match_operand:SI 2 "nonimmediate_operand" "rm,rm")) + (match_operand:SI 2 "nonimmediate_operand" "jrjm,rm")) (match_operand:V2SI 1 "register_operand" "0,Yv") (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE @@ -3971,6 +3978,7 @@ (define_insn "*mmx_pinsrd" } } [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "prefix_extra" "1") (set_attr "type" "sselog") (set_attr "length_immediate" "1") @@ -4031,7 +4039,7 @@ (define_insn "*mmx_pinsrb" [(set (match_operand:V8QI 0 "register_operand" "=x,YW") (vec_merge:V8QI (vec_duplicate:V8QI - (match_operand:QI 2 "nonimmediate_operand" "rm,rm")) + (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm")) (match_operand:V8QI 1 "register_operand" "0,YW") (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE @@ -4057,28 +4065,31 @@ (define_insn "*mmx_pinsrb" } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") + (set_attr "gpr32" "0,1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) (define_insn "*mmx_pextrw" - [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m") + [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,jm,m") (vec_select:HI - (match_operand:V4HI 1 "register_operand" "y,YW,YW") + (match_operand:V4HI 1 "register_operand" "y,YW,YW,YW") (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)" "@ pextrw\t{%2, %1, %k0|%k0, %1, %2} %vpextrw\t{%2, %1, %k0|%k0, %1, %2} - %vpextrw\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "*,sse2,sse4") - (set_attr "mmx_isa" "native,*,*") - (set_attr "type" "mmxcvt,sselog1,sselog1") + pextrw\t{%2, %1, %0|%0, %1, %2} + vpextrw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "*,sse2,sse4_noavx,avx") + (set_attr "gpr32" "1,1,0,1") + (set_attr "mmx_isa" "native,*,*,*") + (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1") (set_attr "length_immediate" "1") - (set_attr "prefix" "orig,maybe_vex,maybe_vex") - (set_attr "mode" "DI,TI,TI")]) + (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex") + (set_attr "mode" "DI,TI,TI,TI")]) (define_insn "*mmx_pextrw_zext" [(set (match_operand:SWI48 0 "register_operand" "=r,r") @@ -4099,29 +4110,34 @@ (define_insn "*mmx_pextrw_zext" (set_attr "mode" "DI,TI")]) (define_insn "*mmx_pextrb" - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m") + [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m") (vec_select:QI - (match_operand:V8QI 1 "register_operand" "YW,YW") + (match_operand:V8QI 1 "register_operand" "YW,YW,YW,YW") (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "@ - %vpextrb\t{%2, %1, %k0|%k0, %1, %2} - %vpextrb\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog1") + pextrb\t{%2, %1, %k0|%k0, %1, %2} + pextrb\t{%2, %1, %0|%0, %1, %2} + vpextrb\t{%2, %1, %k0|%k0, %1, %2} + vpextrb\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,noavx,avx,avx") + (set_attr "gpr32" "1,0,1,1") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) (define_insn "*mmx_pextrb_zext" - [(set (match_operand:SWI248 0 "register_operand" "=r") + [(set (match_operand:SWI248 0 "register_operand" "=jr,r") (zero_extend:SWI248 (vec_select:QI - (match_operand:V8QI 1 "register_operand" "YW") + (match_operand:V8QI 1 "register_operand" "YW,YW") (parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -4131,13 +4147,14 @@ (define_insn "mmx_pshufbv8qi3" [(set (match_operand:V8QI 0 "register_operand" "=x,Yw") (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,Yw") - (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")] + (match_operand:V16QI 2 "vector_operand" "xja,Ywm")] UNSPEC_PSHUFB))] "TARGET_SSSE3 && TARGET_MMX_WITH_SSE" "@ pshufb\t{%2, %0|%0, %2} vpshufb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") @@ -4148,13 +4165,14 @@ (define_insn "mmx_pshufbv4qi3" [(set (match_operand:V4QI 0 "register_operand" "=x,Yw") (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "0,Yw") - (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")] + (match_operand:V16QI 2 "vector_operand" "xja,Ywm")] UNSPEC_PSHUFB))] "TARGET_SSSE3" "@ pshufb\t{%2, %0|%0, %2} vpshufb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") @@ -4414,29 +4432,31 @@ (define_split ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.cc (define_insn "*vec_extractv2si_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=y,rm,x,x,y,x,r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=y,jrjm,rm,x,x,y,x,r") (vec_select:SI - (match_operand:V2SI 1 "nonimmediate_operand" " 0,x ,x,0,o,o,o") + (match_operand:V2SI 1 "nonimmediate_operand" " 0,x, x ,x,0,o,o,o") (parallel [(const_int 1)])))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ punpckhdq\t%0, %0 - %vpextrd\t{$1, %1, %0|%0, %1, 1} + pextrd\t{$1, %1, %0|%0, %1, 1} + vpextrd\t{$1, %1, %0|%0, %1, 1} %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5} shufps\t{$0xe5, %0, %0|%0, %0, 0xe5} # # #" - [(set_attr "isa" "*,sse4,sse2,noavx,*,*,*") - (set_attr "mmx_isa" "native,*,*,*,native,*,*") - (set_attr "type" "mmxcvt,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov") + [(set_attr "isa" "*,sse4_noavx,avx,sse2,noavx,*,*,*") + (set_attr "gpr32" "1,0,1,1,1,1,1,1") + (set_attr "mmx_isa" "native,*,*,*,*,native,*,*") + (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov") (set (attr "length_immediate") - (if_then_else (eq_attr "alternative" "1,2,3") + (if_then_else (eq_attr "alternative" "1,2,3,4") (const_string "1") (const_string "*"))) - (set_attr "prefix" "orig,maybe_vex,maybe_vex,orig,orig,orig,orig") - (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")]) + (set_attr "prefix" "orig,orig,maybe_evex,maybe_vex,orig,orig,orig,orig") + (set_attr "mode" "DI,TI,TI,TI,V4SF,SI,SI,SI")]) (define_split [(set (match_operand:SI 0 "register_operand") @@ -4448,15 +4468,16 @@ (define_split "operands[1] = adjust_address (operands[1], SImode, 4);") (define_insn "*vec_extractv2si_1_zext" - [(set (match_operand:DI 0 "register_operand" "=r") + [(set (match_operand:DI 0 "register_operand" "=jr,r") (zero_extend:DI (vec_select:SI - (match_operand:V2SI 1 "register_operand" "x") + (match_operand:V2SI 1 "register_operand" "x,x") (parallel [(const_int 1)]))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_64BIT && TARGET_SSE4_1" "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}" - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -4606,7 +4627,7 @@ (define_insn "*pinsrb" [(set (match_operand:V4QI 0 "register_operand" "=x,YW") (vec_merge:V4QI (vec_duplicate:V4QI - (match_operand:QI 2 "nonimmediate_operand" "rm,rm")) + (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm")) (match_operand:V4QI 1 "register_operand" "0,YW") (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE4_1 @@ -4631,6 +4652,7 @@ (define_insn "*pinsrb" } } [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") @@ -4638,15 +4660,17 @@ (define_insn "*pinsrb" (set_attr "mode" "TI")]) (define_insn "*pextrw" - [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,m") + [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,jm,m") (vec_select:HI - (match_operand:V2HI 1 "register_operand" "YW,YW") + (match_operand:V2HI 1 "register_operand" "YW,YW,YW") (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))] "TARGET_SSE2" "@ %vpextrw\t{%2, %1, %k0|%k0, %1, %2} - %vpextrw\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "*,sse4") + pextrw\t{%2, %1, %0|%0, %1, %2} + vpextrw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "*,sse4_noavx,avx") + (set_attr "gpr32" "1,0,1") (set_attr "type" "sselog1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -4666,29 +4690,34 @@ (define_insn "*pextrw_zext" (set_attr "mode" "TI")]) (define_insn "*pextrb" - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m") + [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m") (vec_select:QI - (match_operand:V4QI 1 "register_operand" "YW,YW") + (match_operand:V4QI 1 "register_operand" "YW,YW,YW,YW") (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] "TARGET_SSE4_1" "@ - %vpextrb\t{%2, %1, %k0|%k0, %1, %2} - %vpextrb\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sselog1") + pextrb\t{%2, %1, %k0|%k0, %1, %2} + pextrb\t{%2, %1, %0|%0, %1, %2} + vpextrb\t{%2, %1, %k0|%k0, %1, %2} + vpextrb\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,noavx,avx,avx") + (set_attr "gpr32" "1,0,1,1") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) (define_insn "*pextrb_zext" - [(set (match_operand:SWI248 0 "register_operand" "=r") + [(set (match_operand:SWI248 0 "register_operand" "=jr,r") (zero_extend:SWI248 (vec_select:QI - (match_operand:V4QI 1 "register_operand" "YW") + (match_operand:V4QI 1 "register_operand" "YW,YW") (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))] "TARGET_SSE4_1" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4db3940e422..d3b59c4866b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -10836,7 +10836,7 @@ (define_insn "*vec_concatv2sf_sse4_1" (match_operand:SF 1 "nonimmediate_operand" " 0, 0,Yv, 0,0, v,m, 0 , m") (match_operand:SF 2 "nonimm_or_0_operand" - " Yr,*x,Yv, m,m, m,C,*ym, C")))] + " Yr,*x,Yv, jm,jm, m,C,*ym, C")))] "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ unpcklps\t{%2, %0|%0, %2} @@ -10868,6 +10868,10 @@ (define_insn "*vec_concatv2sf_sse4_1" (if_then_else (eq_attr "alternative" "7,8") (const_string "native") (const_string "*"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "3,4") + (const_string "0") + (const_string "1"))) (set (attr "prefix_data16") (if_then_else (eq_attr "alternative" "3,4") (const_string "1") @@ -10959,7 +10963,7 @@ (define_insn "vec_set_0" (vec_merge:VI4F_128 (vec_duplicate:VI4F_128 (match_operand: 2 "general_operand" - " Yr,*x,v,m,r ,m,x,v,?rm,?rm,?rm,!x,?re,!*fF")) + " Yr,*x,v,m,r ,m,x,v,?jrjm,?jrjm,?rm,!x,?re,!*fF")) (match_operand:VI4F_128 1 "nonimm_or_0_operand" " C , C,C,C,C ,C,0,v,0 ,0 ,x ,0 ,0 ,0") (const_int 1)))] @@ -10999,6 +11003,10 @@ (define_insn "vec_set_0" (const_string "fmov") ] (const_string "ssemov"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "8,9") + (const_string "0") + (const_string "1"))) (set (attr "prefix_extra") (if_then_else (eq_attr "alternative" "8,9,10") (const_string "1") @@ -11169,7 +11177,7 @@ (define_insn "*vec_setv4sf_sse4_1" [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (match_operand:SF 2 "nonimmediate_operand" "Yrm,*xm,vm")) + (match_operand:SF 2 "nonimmediate_operand" "Yrjm,*xjm,vm")) (match_operand:V4SF 1 "register_operand" "0,0,v") (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE4_1 @@ -11190,6 +11198,7 @@ (define_insn "*vec_setv4sf_sse4_1" } [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sselog") + (set_attr "gpr32" "0,0,1") (set_attr "prefix_data16" "1,1,*") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") @@ -11264,7 +11273,7 @@ (define_insn_and_split "*vec_setv2di_0_zero_extendsi_1" (define_insn "@sse4_1_insertps_" [(set (match_operand:VI4F_128 0 "register_operand" "=Yr,*x,v") (unspec:VI4F_128 - [(match_operand:VI4F_128 2 "nonimmediate_operand" "Yrm,*xm,vm") + [(match_operand:VI4F_128 2 "nonimmediate_operand" "Yrjm,*xjm,vm") (match_operand:VI4F_128 1 "register_operand" "0,0,v") (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_INSERTPS))] @@ -11290,6 +11299,7 @@ (define_insn "@sse4_1_insertps_" } } [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,1,*") (set_attr "prefix_extra" "1") @@ -11367,7 +11377,7 @@ (define_insn_and_split "*vec_extractv4sf_0" "operands[1] = gen_lowpart (SFmode, operands[1]);") (define_insn_and_split "*sse4_1_extractps" - [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv") + [(set (match_operand:SF 0 "nonimmediate_operand" "=jrjm,jrjm,rm,Yv,Yv") (vec_select:SF (match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v") (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] @@ -11401,6 +11411,7 @@ (define_insn_and_split "*sse4_1_extractps" DONE; } [(set_attr "isa" "noavx,noavx,avx,noavx,avx") + (set_attr "gpr32" "0,0,1,1,1") (set_attr "type" "sselog,sselog,sselog,*,*") (set_attr "prefix_data16" "1,1,1,*,*") (set_attr "prefix_extra" "1,1,1,*,*") @@ -12265,9 +12276,9 @@ (define_insn_and_split "*vec_extract_0" "operands[1] = gen_lowpart (mode, operands[1]);") (define_insn "*vec_extract" - [(set (match_operand:HFBF 0 "register_sse4nonimm_operand" "=?r,m,x,v") + [(set (match_operand:HFBF 0 "register_sse4nonimm_operand" "=?r,jm,m,x,v") (vec_select:HFBF - (match_operand: 1 "register_operand" "v,v,0,v") + (match_operand: 1 "register_operand" "v,x,v,0,v") (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))] "TARGET_SSE2" @@ -12277,12 +12288,14 @@ (define_insn "*vec_extract" case 0: return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"; case 1: - return "%vpextrw\t{%2, %1, %0|%0, %1, %2}"; - + return "pextrw\t{%2, %1, %0|%0, %1, %2}"; case 2: + return "vpextrw\t{%2, %1, %0|%0, %1, %2}"; + + case 3: operands[2] = GEN_INT (INTVAL (operands[2]) * 2); return "psrldq\t{%2, %0|%0, %2}"; - case 3: + case 4: operands[2] = GEN_INT (INTVAL (operands[2]) * 2); return "vpsrldq\t{%2, %1, %0|%0, %1, %2}"; @@ -12290,8 +12303,9 @@ (define_insn "*vec_extract" gcc_unreachable (); } } - [(set_attr "isa" "*,sse4,noavx,avx") - (set_attr "type" "sselog1,sselog1,sseishft1,sseishft1") + [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx") + (set_attr "gpr32" "1,0,1,1,1") + (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1") (set_attr "prefix" "maybe_evex") (set_attr "mode" "TI")]) @@ -15653,7 +15667,7 @@ (define_insn "*sse4_1_mulv2siv2di3" (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm") + (match_operand:V4SI 2 "vector_operand" "Yrja,*xja,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1 && && !(MEM_P (operands[1]) && MEM_P (operands[2]))" @@ -15662,6 +15676,7 @@ (define_insn "*sse4_1_mulv2siv2di3" pmuldq\t{%2, %0|%0, %2} vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "sseimul") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,vex") @@ -15899,7 +15914,7 @@ (define_insn "*_mul3" [(set (match_operand:VI4_AVX512F 0 "register_operand" "=Yr,*x,v") (mult:VI4_AVX512F (match_operand:VI4_AVX512F 1 "bcst_vector_operand" "%0,0,v") - (match_operand:VI4_AVX512F 2 "bcst_vector_operand" "YrBm,*xBm,vmBr")))] + (match_operand:VI4_AVX512F 2 "bcst_vector_operand" "Yrja,*xja,vmBr")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, mode, operands) && " "@ @@ -15907,6 +15922,7 @@ (define_insn "*_mul3" pmulld\t{%2, %0|%0, %2} vpmulld\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "sseimul") (set_attr "prefix_extra" "1") (set_attr "prefix" "") @@ -16711,7 +16727,7 @@ (define_insn "*sse4_1_3" [(set (match_operand:VI14_128 0 "register_operand" "=Yr,*x,") (smaxmin:VI14_128 (match_operand:VI14_128 1 "vector_operand" "%0,0,") - (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,m")))] + (match_operand:VI14_128 2 "vector_operand" "Yrja,*xja,m")))] "TARGET_SSE4_1 && && !(MEM_P (operands[1]) && MEM_P (operands[2]))" @@ -16722,6 +16738,7 @@ (define_insn "*sse4_1_3" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") + (set_attr "gpr32" "0,0,1") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -16729,13 +16746,14 @@ (define_insn "*v8hi3" [(set (match_operand:V8HI 0 "register_operand" "=x,Yw") (smaxmin:V8HI (match_operand:V8HI 1 "vector_operand" "%0,Yw") - (match_operand:V8HI 2 "vector_operand" "xBm,Ywm")))] + (match_operand:V8HI 2 "vector_operand" "xja,Ywm")))] "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pw\t{%2, %0|%0, %2} vpw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") + (set_attr "gpr32" "0,1") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -16803,6 +16821,7 @@ (define_insn "*sse4_1_3" vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseiadd") + (set_attr "gpr32" "0,0,1") (set_attr "prefix_extra" "1,1,*") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "TI")]) @@ -16811,12 +16830,13 @@ (define_insn "*v16qi3" [(set (match_operand:V16QI 0 "register_operand" "=x,Yw") (umaxmin:V16QI (match_operand:V16QI 1 "vector_operand" "%0,Yw") - (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")))] + (match_operand:V16QI 2 "vector_operand" "xja,Ywm")))] "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pb\t{%2, %0|%0, %2} vpb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sseiadd") (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) @@ -18808,7 +18828,7 @@ (define_insn "_pinsr" [(set (match_operand:PINSR_MODE 0 "register_operand" "=x,x,x,x,v,v,&x") (vec_merge:PINSR_MODE (vec_duplicate:PINSR_MODE - (match_operand: 2 "nonimmediate_operand" "r,m,r,m,r,m,x")) + (match_operand: 2 "nonimmediate_operand" "jr,jm,r,m,r,m,x")) (match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x,v,v,x") (match_operand:SI 3 "const_int_operand")))] "TARGET_SSE2 @@ -18845,6 +18865,7 @@ (define_insn "_pinsr" } [(set_attr "isa" "noavx,noavx,avx,avx,,,avx2") (set_attr "type" "sselog") + (set_attr "gpr32" "0,0,1,1,1,1,1") (set (attr "prefix_rex") (if_then_else (and (not (match_test "TARGET_AVX")) @@ -20005,17 +20026,23 @@ (define_insn_and_split "*vec_extract_0_mem" operands[4] = gen_lowpart (mode, operands[2]); }) +(define_mode_attr vi128_jr_r + [(V16QI "jr") (V8HI "r")]) + (define_insn "*vec_extract" - [(set (match_operand: 0 "register_sse4nonimm_operand" "=r,m") + [(set (match_operand: 0 "register_sse4nonimm_operand" "=,r,jm,m") (vec_select: - (match_operand:PEXTR_MODE12 1 "register_operand" "YW,YW") + (match_operand:PEXTR_MODE12 1 "register_operand" "YW,YW,YW,YW") (parallel [(match_operand:SI 2 "const_0_to__operand")])))] "TARGET_SSE2" "@ - %vpextr\t{%2, %1, %k0|%k0, %1, %2} - %vpextr\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "*,sse4") + pextr\t{%2, %1, %k0|%k0, %1, %2} + vpextr\t{%2, %1, %k0|%k0, %1, %2} + pextr\t{%2, %1, %0|%0, %1, %2} + vpextr\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "sse2_noavx,avx,sse4_noavx,avx") + (set_attr "gpr32" "1,1,0,1") (set_attr "type" "sselog1") (set (attr "prefix_extra") (if_then_else @@ -20023,20 +20050,21 @@ (define_insn "*vec_extract" (const_string "*") (const_string "1"))) (set_attr "length_immediate" "1") - (set_attr "prefix" "maybe_vex,maybe_vex") + (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) (define_insn "*vec_extract_zext" - [(set (match_operand:SWI48 0 "register_operand" "=r") + [(set (match_operand:SWI48 0 "register_operand" "=,r") (zero_extend:SWI48 (vec_select: - (match_operand:PEXTR_MODE12 1 "register_operand" "YW") + (match_operand:PEXTR_MODE12 1 "register_operand" "YW,YW") (parallel [(match_operand:SI 2 "const_0_to__operand")]))))] "TARGET_SSE2" "%vpextr\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set (attr "prefix_extra") (if_then_else (eq (const_string "mode") (const_string "V8HImode")) @@ -20047,15 +20075,16 @@ (define_insn "*vec_extract_zext" (set_attr "mode" "TI")]) (define_insn "*vec_extractv16qi_zext" - [(set (match_operand:HI 0 "register_operand" "=r") + [(set (match_operand:HI 0 "register_operand" "=jr,r") (zero_extend:HI (vec_select:QI - (match_operand:V16QI 1 "register_operand" "YW") + (match_operand:V16QI 1 "register_operand" "YW,YW") (parallel [(match_operand:SI 2 "const_0_to_15_operand")]))))] "TARGET_SSE4_1" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") @@ -20161,24 +20190,26 @@ (define_split "operands[1] = gen_lowpart (SImode, operands[1]);") (define_insn "*vec_extractv4si" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,Yw") + [(set (match_operand:SI 0 "nonimmediate_operand" "=jrjm,rm,rm,Yr,*x,Yw") (vec_select:SI - (match_operand:V4SI 1 "register_operand" " x, v, 0, 0,Yw") + (match_operand:V4SI 1 "register_operand" "x, x, v, 0, 0, Yw") (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] "TARGET_SSE4_1" { switch (which_alternative) { case 0: + return "pextrd\t{%2, %1, %0|%0, %1, %2}"; case 1: - return "%vpextrd\t{%2, %1, %0|%0, %1, %2}"; - case 2: + return "vpextrd\t{%2, %1, %0|%0, %1, %2}"; + case 3: + case 4: operands[2] = GEN_INT (INTVAL (operands[2]) * 4); return "psrldq\t{%2, %0|%0, %2}"; - case 4: + case 5: operands[2] = GEN_INT (INTVAL (operands[2]) * 4); return "vpsrldq\t{%2, %1, %0|%0, %1, %2}"; @@ -20186,25 +20217,26 @@ (define_insn "*vec_extractv4si" gcc_unreachable (); } } - [(set_attr "isa" "*,avx512dq,noavx,noavx,avx") - (set_attr "type" "sselog1,sselog1,sseishft1,sseishft1,sseishft1") + [(set_attr "isa" "noavx,avx,avx512dq,noavx,noavx,avx") + (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1") + (set_attr "gpr32" "0,1,1,1,1,1") (set (attr "prefix_extra") (if_then_else (eq_attr "alternative" "0,1") (const_string "1") (const_string "*"))) (set_attr "length_immediate" "1") - (set_attr "prefix" "maybe_vex,evex,orig,orig,maybe_vex") + (set_attr "prefix" "orig,vex,evex,orig,orig,maybe_vex") (set_attr "mode" "TI")]) (define_insn "*vec_extractv4si_zext" - [(set (match_operand:DI 0 "register_operand" "=r,r") + [(set (match_operand:DI 0 "register_operand" "=jr,r,r") (zero_extend:DI (vec_select:SI - (match_operand:V4SI 1 "register_operand" "x,v") + (match_operand:V4SI 1 "register_operand" "x,x,v") (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))] "TARGET_64BIT && TARGET_SSE4_1" "%vpextrd\t{%2, %1, %k0|%k0, %1, %2}" - [(set_attr "isa" "*,avx512dq") + [(set_attr "isa" "noavx,avx,avx512dq") (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") @@ -20234,13 +20266,14 @@ (define_insn_and_split "*vec_extractv4si_zext_mem" }) (define_insn "*vec_extractv2di_1" - [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm,m,x,x,Yv,x,v,r") + [(set (match_operand:DI 0 "nonimmediate_operand" "=jrjm,rm,rm,m,x,x,Yv,x,v,r") (vec_select:DI - (match_operand:V2DI 1 "nonimmediate_operand" "x ,v ,v,0,x, v,x,o,o") + (match_operand:V2DI 1 "nonimmediate_operand" "x, x ,v ,v,0,x, v,x,o,o") (parallel [(const_int 1)])))] "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ - %vpextrq\t{$1, %1, %0|%0, %1, 1} + pextrq\t{$1, %1, %0|%0, %1, 1} + vpextrq\t{$1, %1, %0|%0, %1, 1} vpextrq\t{$1, %1, %0|%0, %1, 1} %vmovhps\t{%1, %0|%0, %1} psrldq\t{$8, %0|%0, 8} @@ -20251,44 +20284,47 @@ (define_insn "*vec_extractv2di_1" #" [(set (attr "isa") (cond [(eq_attr "alternative" "0") - (const_string "x64_sse4") + (const_string "x64_sse4_noavx") (eq_attr "alternative" "1") + (const_string "x64_avx") + (eq_attr "alternative" "2") (const_string "x64_avx512dq") - (eq_attr "alternative" "3") - (const_string "sse2_noavx") (eq_attr "alternative" "4") - (const_string "avx") + (const_string "sse2_noavx") (eq_attr "alternative" "5") - (const_string "avx512bw") + (const_string "avx") (eq_attr "alternative" "6") - (const_string "noavx") + (const_string "avx512bw") (eq_attr "alternative" "8") + (const_string "noavx") + (eq_attr "alternative" "9") (const_string "x64") ] (const_string "*"))) (set (attr "type") - (cond [(eq_attr "alternative" "2,6,7") + (cond [(eq_attr "alternative" "3,7,8") (const_string "ssemov") - (eq_attr "alternative" "3,4,5") + (eq_attr "alternative" "4,5,6") (const_string "sseishft1") - (eq_attr "alternative" "8") + (eq_attr "alternative" "9") (const_string "imov") ] (const_string "sselog1"))) + (set_attr "gpr32" "0,1,1,1,1,1,1,1,1,1") (set (attr "length_immediate") - (if_then_else (eq_attr "alternative" "0,1,3,4,5") + (if_then_else (eq_attr "alternative" "0,1,2,4,5,6") (const_string "1") (const_string "*"))) (set (attr "prefix_rex") - (if_then_else (eq_attr "alternative" "0,1") + (if_then_else (eq_attr "alternative" "0") (const_string "1") (const_string "*"))) (set (attr "prefix_extra") - (if_then_else (eq_attr "alternative" "0,1") + (if_then_else (eq_attr "alternative" "0") (const_string "1") (const_string "*"))) - (set_attr "prefix" "maybe_vex,evex,maybe_vex,orig,vex,evex,orig,*,*") - (set_attr "mode" "TI,TI,V2SF,TI,TI,TI,V4SF,DI,DI")]) + (set_attr "prefix" "orig,maybe_evex,evex,maybe_vex,orig,vex,evex,orig,*,*") + (set_attr "mode" "TI,TI,TI,V2SF,TI,TI,TI,V4SF,DI,DI")]) (define_split [(set (match_operand: 0 "register_operand") @@ -20406,7 +20442,7 @@ (define_insn "*vec_concatv2si_sse4_1" (match_operand:SI 1 "nonimmediate_operand" " 0, 0, x,Yv, 0, 0,Yv,rm, 0,rm") (match_operand:SI 2 "nonimm_or_0_operand" - " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))] + "jrjm,jrjm,rm,rm,Yr,*x,Yv, C,*ym, C")))] "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pinsrd\t{$1, %2, %0|%0, %2, 1} @@ -20433,6 +20469,10 @@ (define_insn "*vec_concatv2si_sse4_1" (const_string "mmxmov") ] (const_string "sselog"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "0,1") + (const_string "0") + (const_string "1"))) (set (attr "prefix_extra") (if_then_else (eq_attr "alternative" "0,1,2,3") (const_string "1") @@ -20557,7 +20597,7 @@ (define_insn "vec_concatv2di" (match_operand:DI 1 "register_operand" " 0, 0,x ,Yv,0,Yv,0,0,v") (match_operand:DI 2 "nonimmediate_operand" - " rm,rm,rm,rm,x,Yv,x,m,m")))] + " jrm,jrm,rm,rm,x,Yv,x,m,m")))] "TARGET_SSE" "@ pinsrq\t{$1, %2, %0|%0, %2, 1} @@ -20587,6 +20627,10 @@ (define_insn "vec_concatv2di" (eq_attr "alternative" "0,1,2,3,4,5") (const_string "sselog") (const_string "ssemov"))) + (set (attr "gpr32") + (if_then_else (eq_attr "alternative" "0,1") + (const_string "0") + (const_string "1"))) (set (attr "prefix_rex") (if_then_else (eq_attr "alternative" "0,1,2,3") (const_string "1") @@ -21519,7 +21563,7 @@ (define_insn "ssse3_pmaddubsw128" (const_int 12) (const_int 14)]))) (sign_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "vector_operand" "xBm,Ywm") + (match_operand:V16QI 2 "vector_operand" "xja,Ywm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -21542,6 +21586,7 @@ (define_insn "ssse3_pmaddubsw128" pmaddubsw\t{%2, %0|%0, %2} vpmaddubsw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sseiadd") (set_attr "atom_unit" "simul") (set_attr "prefix_extra" "1") @@ -21660,7 +21705,7 @@ (define_insn "*_pmulhrsw3" (sign_extend: (match_operand:VI2_AVX2_AVX512BW 1 "vector_operand" "%0,")) (sign_extend: - (match_operand:VI2_AVX2_AVX512BW 2 "vector_operand" "xBm,m"))) + (match_operand:VI2_AVX2_AVX512BW 2 "vector_operand" "xja,m"))) (const_int 14)) (match_operand:VI2_AVX2_AVX512BW 3 "const1_operand")) (const_int 1))))] @@ -21670,6 +21715,7 @@ (define_insn "*_pmulhrsw3" pmulhrsw\t{%2, %0|%0, %2} vpmulhrsw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sseimul") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") @@ -21786,13 +21832,14 @@ (define_insn "_pshufb3" [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,") (unspec:VI1_AVX512 [(match_operand:VI1_AVX512 1 "register_operand" "0,") - (match_operand:VI1_AVX512 2 "vector_operand" "xBm,m")] + (match_operand:VI1_AVX512 2 "vector_operand" "xja,m")] UNSPEC_PSHUFB))] "TARGET_SSSE3 && && " "@ pshufb\t{%2, %0|%0, %2} vpshufb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") @@ -21908,7 +21955,7 @@ (define_insn "_palignr" [(set (match_operand:VIMAX_AVX2_AVX512BW 0 "register_operand" "=x,") (unspec:VIMAX_AVX2_AVX512BW [(match_operand:VIMAX_AVX2_AVX512BW 1 "register_operand" "0,") - (match_operand:VIMAX_AVX2_AVX512BW 2 "vector_operand" "xBm,m") + (match_operand:VIMAX_AVX2_AVX512BW 2 "vector_operand" "xja,m") (match_operand:SI 3 "const_0_to_255_mul_8_operand")] UNSPEC_PALIGNR))] "TARGET_SSSE3" @@ -21926,6 +21973,7 @@ (define_insn "_palignr" } } [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "type" "sseishft") (set_attr "atom_unit" "sishuf") (set_attr "prefix_extra" "1") @@ -22000,6 +22048,7 @@ (define_insn_and_split "ssse3_palignrdi" } [(set_attr "mmx_isa" "native,sse_noavx,avx") (set_attr "type" "sseishft") + (set_attr "gpr32" "0,0,1") (set_attr "atom_unit" "sishuf") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") @@ -22015,12 +22064,14 @@ (define_mode_iterator VI1248_AVX512VL_AVX512BW (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_insn "*abs2" - [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand" "=") + [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand" "=x,") (abs:VI1248_AVX512VL_AVX512BW - (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand" "Bm")))] + (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand" "xja,Bm")))] "TARGET_SSSE3" "%vpabs\t{%1, %0|%0, %1}" - [(set_attr "type" "sselog1") + [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) @@ -22358,11 +22409,12 @@ (define_mode_attr vi8_sse4_1_avx2_avx512 (define_insn "_movntdqa" [(set (match_operand:VI8_AVX2_AVX512F 0 "register_operand" "=Yr,*x,v") - (unspec:VI8_AVX2_AVX512F [(match_operand:VI8_AVX2_AVX512F 1 "memory_operand" "m,m,m")] + (unspec:VI8_AVX2_AVX512F [(match_operand:VI8_AVX2_AVX512F 1 "memory_operand" "jm,jm,m")] UNSPEC_MOVNTDQA))] "TARGET_SSE4_1" "%vmovntdqa\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") @@ -22381,6 +22433,7 @@ (define_insn "_mpsadbw" mpsadbw\t{%3, %2, %0|%0, %2, %3} vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "sselog1") (set_attr "gpr32" "0") (set_attr "length_immediate" "1") @@ -22394,7 +22447,7 @@ (define_insn "_packusdw" [(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=Yr,*x,") (unspec:VI2_AVX2_AVX512BW [(match_operand: 1 "register_operand" "0,0,") - (match_operand: 2 "vector_operand" "YrBm,*xBm,m")] + (match_operand: 2 "vector_operand" "Yrja,*xja,m")] UNSPEC_US_TRUNCATE))] "TARGET_SSE4_1 && && " "@ @@ -22402,6 +22455,7 @@ (define_insn "_packusdw" packusdw\t{%2, %0|%0, %2} vpackusdw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,") @@ -22748,10 +22802,14 @@ (define_insn "sse4_1_v8qiv8hi2" (define_insn "*sse4_1_v8qiv8hi2_1" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,Yw") (any_extend:V8HI - (match_operand:V8QI 1 "memory_operand" "m,m,m")))] + (match_operand:V8QI 1 "memory_operand" "jm,jm,m")))] "TARGET_SSE4_1 && && " - "%vpmovbw\t{%1, %0|%0, %1}" + "@ + pmovbw\t{%1, %0|%0, %1} + pmovbw\t{%1, %0|%0, %1} + vpmovbw\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") @@ -22781,7 +22839,7 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3" [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,Yw") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,Ywm") + (match_operand:V16QI 1 "vector_operand" "Yrja,*xja,Ywm") (match_operand:V16QI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand")])))] @@ -22806,7 +22864,8 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3" DONE; } } - [(set_attr "isa" "noavx,noavx,avx")]) + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1")]) (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4" [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,Yw") @@ -22814,7 +22873,7 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4" (vec_concat:V32QI (subreg:V16QI (vec_concat:VI248_128 - (match_operand: 1 "vector_operand" "YrBm,*xBm,Ywm") + (match_operand: 1 "vector_operand" "Yrja,*xja,Ywm") (match_operand: 2 "const0_operand")) 0) (match_operand:V16QI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" @@ -22841,7 +22900,8 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4" } operands[1] = lowpart_subreg (V16QImode, operands[1], mode); } - [(set_attr "isa" "noavx,noavx,avx")]) + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1")]) (define_expand "v8qiv8hi2" [(set (match_operand:V8HI 0 "register_operand") @@ -22960,10 +23020,11 @@ (define_insn "sse4_1_v4qiv4si2" (define_insn "*sse4_1_v4qiv4si2_1" [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI - (match_operand:V4QI 1 "memory_operand" "m,m,m")))] + (match_operand:V4QI 1 "memory_operand" "jm,jm,m")))] "TARGET_SSE4_1 && " "%vpmovbd\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") @@ -23132,10 +23193,11 @@ (define_insn "sse4_1_v4hiv4si2" (define_insn "*sse4_1_v4hiv4si2_1" [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI - (match_operand:V4HI 1 "memory_operand" "m,m,m")))] + (match_operand:V4HI 1 "memory_operand" "jm,jm,m")))] "TARGET_SSE4_1 && " "%vpmovwd\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") @@ -23184,7 +23246,7 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_3" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm") + (match_operand:V8HI 1 "vector_operand" "Yrja,*xja,vm") (match_operand:V8HI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand")])))] @@ -23207,7 +23269,8 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_3" DONE; } } - [(set_attr "isa" "noavx,noavx,avx")]) + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1")]) (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") @@ -23215,7 +23278,7 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4" (vec_concat:V16HI (subreg:V8HI (vec_concat:VI148_128 - (match_operand: 1 "vector_operand" "YrBm,*xBm,vm") + (match_operand: 1 "vector_operand" "Yrja,*xja,vm") (match_operand: 2 "const0_operand")) 0) (match_operand:V8HI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" @@ -23240,7 +23303,8 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4" } operands[1] = lowpart_subreg (V8HImode, operands[1], mode); } - [(set_attr "isa" "noavx,noavx,avx")]) + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1")]) (define_insn "avx512f_v8qiv8di2" [(set (match_operand:V8DI 0 "register_operand" "=v") @@ -23378,12 +23442,14 @@ (define_insn "sse4_1_v2qiv2di2" (set_attr "mode" "TI")]) (define_insn "*sse4_1_v2qiv2di2_1" - [(set (match_operand:V2DI 0 "register_operand" "=v") + [(set (match_operand:V2DI 0 "register_operand" "=x,v") (any_extend:V2DI - (match_operand:V2QI 1 "memory_operand" "m")))] + (match_operand:V2QI 1 "memory_operand" "jm,m")))] "TARGET_SSE4_1 && " "%vpmovbq\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_evex") (set_attr "mode" "TI")]) @@ -23517,10 +23583,11 @@ (define_insn "sse4_1_v2hiv2di2" (define_insn "*sse4_1_v2hiv2di2_1" [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI - (match_operand:V2HI 1 "memory_operand" "m,m,m")))] + (match_operand:V2HI 1 "memory_operand" "jm,jm,m")))] "TARGET_SSE4_1 && " "%vpmovwq\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") @@ -23682,10 +23749,11 @@ (define_insn "sse4_1_v2siv2di2" (define_insn "*sse4_1_v2siv2di2_1" [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI - (match_operand:V2SI 1 "memory_operand" "m,m,m")))] + (match_operand:V2SI 1 "memory_operand" "jm,jm,m")))] "TARGET_SSE4_1 && " "%vpmovdq\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,orig,maybe_evex") @@ -23712,7 +23780,7 @@ (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_3" [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm") + (match_operand:V4SI 1 "vector_operand" "Yrja,*xja,vm") (match_operand:V4SI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand")])))] @@ -23733,14 +23801,15 @@ (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_3" DONE; } } - [(set_attr "isa" "noavx,noavx,avx")]) + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1")]) (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_4" [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (vec_select:V4SI (vec_concat:V8SI (vec_concat:V4SI - (match_operand:V2SI 1 "vector_operand" "YrBm, *xBm, vm") + (match_operand:V2SI 1 "vector_operand" "Yrja, *xja, vm") (match_operand:V2SI 2 "const0_operand")) (match_operand:V4SI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" @@ -23762,7 +23831,8 @@ (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_4" } operands[1] = lowpart_subreg (V4SImode, operands[1], V2SImode); } - [(set_attr "isa" "noavx,noavx,avx")]) + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "gpr32" "0,0,1")]) (define_expand "v2siv2di2" [(set (match_operand:V2DI 0 "register_operand") @@ -25953,7 +26023,7 @@ (define_insn "xop_vpermil23" (define_insn "aesenc" [(set (match_operand:V2DI 0 "register_operand" "=x,x,v") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")] + (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] UNSPEC_AESENC))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ @@ -25962,6 +26032,7 @@ (define_insn "aesenc" vaesenc\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,aes,avx512vl") (set_attr "type" "sselog1") + (set_attr "gpr32" "0,1,1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex,evex") (set_attr "btver2_decode" "double,double,double") @@ -25970,7 +26041,7 @@ (define_insn "aesenc" (define_insn "aesenclast" [(set (match_operand:V2DI 0 "register_operand" "=x,x,v") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")] + (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] UNSPEC_AESENCLAST))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ @@ -25979,6 +26050,7 @@ (define_insn "aesenclast" vaesenclast\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,aes,avx512vl") (set_attr "type" "sselog1") + (set_attr "gpr32" "0,1,1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex,evex") (set_attr "btver2_decode" "double,double,double") @@ -25987,7 +26059,7 @@ (define_insn "aesenclast" (define_insn "aesdec" [(set (match_operand:V2DI 0 "register_operand" "=x,x,v") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")] + (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] UNSPEC_AESDEC))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ @@ -25996,6 +26068,7 @@ (define_insn "aesdec" vaesdec\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,aes,avx512vl") (set_attr "type" "sselog1") + (set_attr "gpr32" "0,1,1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex,evex") (set_attr "btver2_decode" "double,double,double") @@ -26004,7 +26077,7 @@ (define_insn "aesdec" (define_insn "aesdeclast" [(set (match_operand:V2DI 0 "register_operand" "=x,x,v") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")] + (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] UNSPEC_AESDECLAST))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ @@ -26012,6 +26085,7 @@ (define_insn "aesdeclast" vaesdeclast\t{%2, %1, %0|%0, %1, %2} vaesdeclast\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,aes,avx512vl") + (set_attr "gpr32" "0,1,1") (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex,evex") @@ -26047,7 +26121,7 @@ (define_insn "aeskeygenassist" (define_insn "pclmulqdq" [(set (match_operand:V2DI 0 "register_operand" "=x,x,v") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm") + (match_operand:V2DI 2 "vector_operand" "xja,xm,vm") (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_PCLMUL))] "TARGET_PCLMUL" @@ -26057,6 +26131,7 @@ (define_insn "pclmulqdq" vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "noavx,avx,vpclmulqdqvl") (set_attr "type" "sselog1") + (set_attr "gpr32" "0,1,1") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex,evex") @@ -29403,7 +29478,7 @@ (define_insn "vgf2p8affineinvqb_" [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm") + (match_operand:VI1_AVX512F 2 "vector_operand" "xja,vm") (match_operand 3 "const_0_to_255_operand")] UNSPEC_GF2P8AFFINEINV))] "TARGET_GFNI" @@ -29411,6 +29486,7 @@ (define_insn "vgf2p8affineinvqb_" gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3} vgf2p8affineinvqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) @@ -29419,7 +29495,7 @@ (define_insn "vgf2p8affineqb_" [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm") + (match_operand:VI1_AVX512F 2 "vector_operand" "xja,vm") (match_operand 3 "const_0_to_255_operand")] UNSPEC_GF2P8AFFINE))] "TARGET_GFNI" @@ -29427,6 +29503,7 @@ (define_insn "vgf2p8affineqb_" gf2p8affineqb\t{%3, %2, %0| %0, %2, %3} vgf2p8affineqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) @@ -29435,13 +29512,14 @@ (define_insn "vgf2p8mulb_" [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,v") - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")] + (match_operand:VI1_AVX512F 2 "vector_operand" "xja,vm")] UNSPEC_GF2P8MUL))] "TARGET_GFNI" "@ gf2p8mulb\t{%2, %0| %0, %2} vgf2p8mulb\t{%2, %1, %0| %0, %1, %2}" [(set_attr "isa" "noavx,avx") + (set_attr "gpr32" "0,1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")])