From patchwork Thu Sep 21 10:32:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1837578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n0iDQRzd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RrsD04Zzwz1yh6 for ; Thu, 21 Sep 2023 20:32:32 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9D9843858412 for ; Thu, 21 Sep 2023 10:32:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 8041E3858D39 for ; Thu, 21 Sep 2023 10:32:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8041E3858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695292335; x=1726828335; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KdvZ/9BpBto9OhnzJeDLob/wkHR391acInYm1RVKK8w=; b=n0iDQRzd+5Rau/9+QK5aDA14YeN+o8pN0StCI5Gau2eCSRfbIIfGD1O9 NxcGT9rfjHZtCK6/bI+dfJtAt25J3IdvG4NwvU2QnsOrvLzo6llU0VooZ OuMdpslqVRO1hmvKNCBefUIcRHbTJNR1OAPmfmFCy3HX0dTEyT9WBfl78 xM73cz92Qxc5v9/x+kMnnhwnspWi8tTBIaj/IfL1XdLKvsZYxcGwOdNeS 16MqBVfB0rmL4zYddr7nVwoHA6lmxC33BaGr8/4jPDUSl5Rfj6oQfJ90C 4ajCmgKNRELa0GpV2GzMA5dlQxY6frg2fzSj5A7Wx3Hv/87LDK/HZEL88 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="411426333" X-IronPort-AV: E=Sophos;i="6.03,165,1694761200"; d="scan'208";a="411426333" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 03:32:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="862405203" X-IronPort-AV: E=Sophos;i="6.03,165,1694761200"; d="scan'208";a="862405203" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga002.fm.intel.com with ESMTP; 21 Sep 2023 03:32:11 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 503981005814; Thu, 21 Sep 2023 18:32:10 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Support ceil and ceilf auto-vectorization Date: Thu, 21 Sep 2023 18:32:09 +0800 Message-Id: <20230921103209.819164-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920023059.1728132-1-pan2.li@intel.com> References: <20230920023059.1728132-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to support auto-vectorization for both the ceil and ceilf of math.h. It depends on the -ffast-math option. When we would like to call ceil/ceilf like v2 = ceil (v1), we will convert it into below insn (reference the implementation of llvm). * vfcvt.x.f v3, v1, RUP * vfcvt.f.x v2, v3 However, the floating point value may not need the cvt as above if its mantissa is zero. For example single precision floating point below. +-----------+---------------+ | float | binary layout | +-----------+---------------+ | 8388607.5 | 0x4affffff | | 8388608.0 | 0x4b000000 | | 8388609.0 | 0x4b000001 | +-----------+---------------+ All single floating point great than 8388608.0 will have all zero mantisaa. We leverage vmflt and mask to filter them out in vector and only do the cvt on mask. Befor this patch: math-ceil-1.c:21:1: missed: couldn't vectorize loop ... .L3: flw fa0,0(s0) addi s0,s0,4 addi s1,s1,4 call ceilf fsw fa0,-4(s1) bne s0,s2,.L3 After this patch: ... fsrmi 3 .L4: vfabs.v v0,v1 vmv1r.v v2,v1 vmflt.vv v0,v0,v4 sub a3,a3,a4 vfcvt.x.f.v v3,v1,v0.t vfcvt.f.x.v v2,v3,v0.t vfsgnj.vv v2,v2,v1 bne .L4 .L14: fsrm a6 ret Please note VLS mode is also involved in this patch and covered by the test cases. gcc/ChangeLog: * config/riscv/autovec.md (ceil2): New pattern. * config/riscv/riscv-protos.h (enum insn_flags): New enum type. (enum insn_type): Ditto. (expand_vec_ceil): New function decl. * config/riscv/riscv-v.cc (gen_ceil_const_fp): New function impl. (expand_vec_float_cmp_mask): Ditto. (expand_vec_copysign): Ditto. (expand_vec_ceil): Ditto. * config/riscv/vector-iterators.md: Add VLS mode to VCONVERT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/math-ceil-1.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-2.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-3.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-4.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-3.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-4.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-double.h: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-single.h: New test. * gcc.target/riscv/rvv/autovec/test-math.h: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/autovec.md | 16 +++ gcc/config/riscv/riscv-protos.h | 5 + gcc/config/riscv/riscv-v.cc | 116 ++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 12 ++ .../riscv/rvv/autovec/math-ceil-1.c | 26 ++++ .../riscv/rvv/autovec/math-ceil-2.c | 26 ++++ .../riscv/rvv/autovec/math-ceil-3.c | 28 +++++ .../riscv/rvv/autovec/math-ceil-4.c | 28 +++++ .../riscv/rvv/autovec/math-ceil-run-1.c | 4 + .../riscv/rvv/autovec/math-ceil-run-2.c | 4 + .../riscv/rvv/autovec/math-ceil-run-3.c | 4 + .../riscv/rvv/autovec/math-ceil-run-4.c | 4 + .../riscv/rvv/autovec/math-ceil-run-double.h | 36 ++++++ .../riscv/rvv/autovec/math-ceil-run-single.h | 36 ++++++ .../gcc.target/riscv/rvv/autovec/test-math.h | 40 ++++++ 15 files changed, 385 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-double.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-single.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 493d5745485..36ed839aa5b 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2374,3 +2374,19 @@ (define_expand "avg3_ceil" riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops3); DONE; }) + +;; ------------------------------------------------------------------------- +;; ---- [FP] Math.h. +;; ------------------------------------------------------------------------- +;; Includes: +;; - ceil/ceilf +;; ------------------------------------------------------------------------- +(define_expand "ceil2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR" + { + riscv_vector::expand_vec_ceil (operands[0], operands[1], mode, mode); + DONE; + } +) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5a2d218d67b..7488a9392de 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -250,6 +250,9 @@ enum insn_flags : unsigned int /* flags for the floating-point rounding mode. */ /* Means INSN has FRM operand and the value is FRM_DYN. */ FRM_DYN_P = 1 << 15, + + /* Means INSN has FRM operand and the value is FRM_RUP. */ + FRM_RUP_P = 1 << 16, }; enum insn_type : unsigned int @@ -290,6 +293,7 @@ enum insn_type : unsigned int UNARY_OP_TAMA = __MASK_OP_TAMA | UNARY_OP_P, UNARY_OP_TAMU = __MASK_OP_TAMU | UNARY_OP_P, UNARY_OP_FRM_DYN = UNARY_OP | FRM_DYN_P, + UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P, /* Binary operator. */ BINARY_OP = __NORMAL_OP | BINARY_OP_P, @@ -428,6 +432,7 @@ bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); void expand_cond_len_unop (unsigned, rtx *); void expand_cond_len_binop (unsigned, rtx *); void expand_reduction (unsigned, unsigned, rtx *, rtx); +void expand_vec_ceil (rtx, rtx, machine_mode, machine_mode); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, bool, void (*)(rtx *, rtx)); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a9287e5d671..9a2cd62c878 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -323,6 +323,8 @@ public: /* Add rounding mode operand. */ if (m_insn_flags & FRM_DYN_P) add_rounding_mode_operand (FRM_DYN); + if (m_insn_flags & FRM_RUP_P) + add_rounding_mode_operand (FRM_RUP); gcc_assert (insn_data[(int) icode].n_operands == m_opno); expand (icode, any_mem_p); @@ -3405,4 +3407,118 @@ cmp_lmul_gt_one (machine_mode mode) return false; } +/* We don't have to convert the floating point to integer when the + mantissa is zero. Thus, ther will be a limitation for both the + single and double precision floating point. There will be no + mantissa if the floating point is greater than the limit. + + 1. Single floating point. + +-----------+---------------+ + | float | binary layout | + +-----------+---------------+ + | 8388607.5 | 0x4affffff | + +-----------+---------------+ + | 8388608.0 | 0x4b000000 | + +-----------+---------------+ + | 8388609.0 | 0x4b000001 | + +-----------+---------------+ + | ... | ... | + + All single floating point will be unchanged for ceil if it is + greater than and equal to 8388608. + + 2. Double floating point. + +--------------------+--------------------+ + | float | binary layout | + +--------------------+--------------------+ + | 4503599627370495.5 | 0X432fffffffffffff | + +--------------------+--------------------+ + | 4503599627370496.0 | 0X4330000000000000 | + +--------------------+--------------------+ + | 4503599627370497.0 | 0X4340000000000000 | + +--------------------+--------------------+ + | ... | ... | + + All double floating point will be unchanged for ceil if it is + greater than and equal to 4503599627370496. + */ +static rtx +gen_ceil_const_fp (machine_mode inner_mode) +{ + REAL_VALUE_TYPE real; + + if (inner_mode == E_SFmode) + real_from_integer (&real, inner_mode, 8388608, SIGNED); + else if (inner_mode == E_DFmode) + real_from_integer (&real, inner_mode, 4503599627370496, SIGNED); + else + gcc_unreachable (); + + return const_double_from_real_value (real, inner_mode); +} + +static rtx +expand_vec_float_cmp_mask (rtx fp_vector, rtx_code code, rtx fp_scalar, + machine_mode vec_fp_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + rtx tmp = gen_reg_rtx (vec_fp_mode); + rtx abs_ops[] = {tmp, fp_vector}; + insn_code icode = code_for_pred (ABS, vec_fp_mode); + emit_vlmax_insn (icode, UNARY_OP, abs_ops); + + /* Step-2: Prepare the scalar float compare register. */ + rtx fp_reg = gen_reg_rtx (GET_MODE_INNER (vec_fp_mode)); + emit_insn (gen_move_insn (fp_reg, fp_scalar)); + + /* Step-3: Prepare the vector float compare register. */ + rtx vec_dup = gen_reg_rtx (vec_fp_mode); + icode = code_for_pred_broadcast (vec_fp_mode); + rtx vfmv_ops[] = {vec_dup, fp_reg}; + emit_vlmax_insn (icode, UNARY_OP, vfmv_ops); + + /* Step-4: Generate the mask. */ + machine_mode mask_mode = get_mask_mode (vec_fp_mode); + rtx mask = gen_reg_rtx (mask_mode); + expand_vec_cmp (mask, code, tmp, vec_dup); + + return mask; +} + +static void +expand_vec_copysign (rtx op_dest, rtx op_src_0, rtx op_src_1, + machine_mode vec_mode) +{ + rtx sgnj_ops[] = {op_dest, op_src_0, op_src_1}; + insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, vec_mode); + + emit_vlmax_insn (icode, BINARY_OP, sgnj_ops); +} + +void +expand_vec_ceil (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Generate the mask on const fp. */ + rtx const_fp = gen_ceil_const_fp (GET_MODE_INNER (vec_fp_mode)); + rtx mask = expand_vec_float_cmp_mask (op_1, LT, const_fp, vec_fp_mode); + + /* Step-2: Convert to integer on mask, with rounding up (aka ceil). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + rtx cvt_x_ops[] = {tmp, mask, tmp, op_1}; + insn_code icode = code_for_pred_fcvt_x_f (UNSPEC_VFCVT, vec_fp_mode); + emit_vlmax_insn (icode, UNARY_OP_TAMU_FRM_RUP, cvt_x_ops); + + /* Step-3: Convert to floating-point on mask for the final result. + To avoid unnecessary frm register access, we use RUP here and it will + never do the rounding up because the tmp rtx comes from the float + to int conversion. */ + rtx cvt_fp_ops[] = {op_0, mask, op_1, tmp}; + icode = code_for_pred (FLOAT, vec_fp_mode); + emit_vlmax_insn (icode, UNARY_OP_TAMU_FRM_RUP, cvt_fp_ops); + + /* Step-4: Retrieve the sign bit. */ + expand_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 0b395e65228..78f08cb4c40 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2339,6 +2339,18 @@ (define_mode_attr VCONVERT [ (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI") (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI") (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI") + + (V1HF "V1HI") (V2HF "V2HI") (V4HF "V4HI") (V8HF "V8HI") (V16HF "V16HI") + (V32HF "V32HI") (V64HF "V64HI") (V128HF "V128HI") (V256HF "V256HI") + (V512HF "V512HI") (V1024HF "V1024HI") (V2048HF "V2048HI") + + (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI") + (V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI") + (V512SF "V512SI") (V1024SF "V1024SI") + + (V1DF "V1DI") (V2DF "V2DI") (V4DF "V4DI") (V8DF "V8DI") (V16DF "V16DI") + (V32DF "V32DI") (V64DF "V64DI") (V128DF "V128DI") (V256DF "V256DI") + (V512DF "V512DI") ]) (define_mode_attr vconvert [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c new file mode 100644 index 00000000000..10d6ec7458e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float_ceilf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** ... +** vmflt\.vv\s+v0,\s*v[0-9]+,\s*v[0-9]+ +** ... +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** ... +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_CEIL(float, ceilf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-2.c new file mode 100644 index 00000000000..f4b6d2d6a9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double_ceil: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** ... +** vmflt\.vv\s+v0,\s*v[0-9]+,\s*v[0-9]+ +** ... +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** ... +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_CEIL(double, ceil) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-3.c new file mode 100644 index 00000000000..bdbcd97f8c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-3.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float_ceilf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** ... +** vmflt\.vv\s+v0,\s*v[0-9]+,\s*v[0-9]+ +** ... +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** ... +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_COND_CEIL(float, ceilf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-4.c new file mode 100644 index 00000000000..5ce313d567b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double_ceil: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** ... +** vmflt\.vv\s+v0,\s*v[0-9]+,\s*v[0-9]+ +** ... +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** ... +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +** fsrm\s+[atx][0-9]+ +** ... +*/ +TEST_COND_CEIL(double, ceil) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-1.c new file mode 100644 index 00000000000..7de1dfe8fe5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-1.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -lm" } */ + +#include "math-ceil-run-single.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-2.c new file mode 100644 index 00000000000..a98aa6ed2fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-2.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -lm" } */ + +#include "math-ceil-run-double.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-3.c new file mode 100644 index 00000000000..025d251dd08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-3.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -lm" } */ + +#include "math-ceil-run-single.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-4.c new file mode 100644 index 00000000000..0dacfe763d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -lm" } */ + +#include "math-ceil-run-double.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-double.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-double.h new file mode 100644 index 00000000000..5b85c007046 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-double.h @@ -0,0 +1,36 @@ +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_CEIL (double, ceil) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 2.0, 1) +TEST_INIT (double, -1.2, -1.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370496.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370495.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + RUN_TEST (double, 1, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, ceil, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, ceil, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-single.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-single.h new file mode 100644 index 00000000000..7b710715d53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-run-single.h @@ -0,0 +1,36 @@ +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_CEIL (float, ceilf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 2.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388608.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + RUN_TEST (float, 1, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, ceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, ceilf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h new file mode 100644 index 00000000000..c3e3f1b24db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h @@ -0,0 +1,40 @@ +#include + +#define TEST_CEIL(TYPE, CALL) \ + void test_##TYPE##_##CALL (TYPE *out, TYPE *in, unsigned count) \ + { \ + for (unsigned i = 0; i < count; i++) \ + out[i] = CALL (in[i]); \ + } + +#define TEST_COND_CEIL(TYPE, CALL) \ + void test_##TYPE##_##CALL (TYPE *out, int *cond, TYPE *in, unsigned count) \ + { \ + for (unsigned i = 0; i < count; i++) \ + out[i] = cond[i] ? CALL (in[i]) : in[i]; \ + } + +#define TEST_INIT(TYPE, VAL_IN, VAL_REF, NUM) \ + void test_##TYPE##_init_##NUM (TYPE *in, TYPE *ref, unsigned size) \ + { \ + for (unsigned i = 0; i < size; i++) \ + { \ + in[i] = VAL_IN; \ + ref[i] = VAL_REF; \ + } \ + } + +#define TEST_ASSERT(TYPE) \ + void test_##TYPE##_assert (TYPE *out, TYPE *ref, unsigned size) \ + { \ + for (unsigned i = 0; i < size; i++) \ + { \ + if (out[i] != ref[i]) \ + __builtin_abort (); \ + } \ + } + +#define RUN_TEST(TYPE, NUM, CALL, IN, OUT, REF, SIZE) \ + test_##TYPE##_init_##NUM (IN, REF, SIZE); \ + test_##TYPE##_##CALL (OUT, IN, SIZE); \ + test_##TYPE##_assert (OUT, REF, SIZE);