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Wed, 06 Sep 2023 10:50:39 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f8-20020aa782c8000000b00687a4b70d1esm11017428pfn.218.2023.09.06.10.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 10:50:39 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Date: Wed, 6 Sep 2023 10:50:22 -0700 Message-ID: <20230906175025.935887-5-ewlu@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230906175025.935887-1-ewlu@rivosinc.com> References: <20230906175025.935887-1-ewlu@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds types to riscv instructions that were added or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html gcc/ChangeLog: * config/riscv/riscv.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c329f55db43..c1cecd27815 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32" "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA" "fmv.x.w\t%0,%1" [(set_attr "move_type" "fmove") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32" "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA" "fmvh.x.d\t%0,%1" [(set_attr "move_type" "fmove") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "movdfsisi3_rv32" @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32" "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA" "fmvp.d.x\t%0,%2,%1" [(set_attr "move_type" "fmove") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_split