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Thu, 31 Aug 2023 10:36:50 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id f4-20020aa782c4000000b0068be7119e55sm1559020pfn.122.2023.08.31.10.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 10:36:49 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V Add Types to Un-Typed Thead Instructions: Date: Thu, 31 Aug 2023 10:36:26 -0700 Message-ID: <20230831173637.583424-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/ This patch updates the THEAD instructions to ensure that no insn is left without a type attribute. Tested for regressions using rv32/64 multilib for linux/newlib. gcc/Changelog: * config/riscv/thead.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/thead.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 29f98dec3a8..6e63cb946e4 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -169,6 +169,7 @@ (define_insn "th_fmv_hw_w_x" "!TARGET_64BIT && TARGET_XTHEADFMV" "fmv.w.x\t%0,%2\n\tth.fmv.hw.x\t%0,%1" [(set_attr "move_type" "move") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "th_fmv_x_w" @@ -178,6 +179,7 @@ (define_insn "th_fmv_x_w" "!TARGET_64BIT && TARGET_XTHEADFMV" "fmv.x.w\t%0,%1" [(set_attr "move_type" "move") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "th_fmv_x_hw" @@ -187,6 +189,7 @@ (define_insn "th_fmv_x_hw" "!TARGET_64BIT && TARGET_XTHEADFMV" "th.fmv.x.hw\t%0,%1" [(set_attr "move_type" "move") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) ;; XTheadMac @@ -322,6 +325,7 @@ (define_insn "*th_mempair_load_2" && th_mempair_operands_p (operands, true, mode)" { return th_mempair_output_move (operands, true, mode, UNKNOWN); } [(set_attr "move_type" "load") + (set_attr "type" "load") (set_attr "mode" "")]) ;; MEMPAIR store 64/32 bit @@ -334,6 +338,7 @@ (define_insn "*th_mempair_store_2" && th_mempair_operands_p (operands, false, mode)" { return th_mempair_output_move (operands, false, mode, UNKNOWN); } [(set_attr "move_type" "store") + (set_attr "type" "store") (set_attr "mode" "")]) ;; MEMPAIR load DI extended signed SI @@ -346,6 +351,7 @@ (define_insn "*th_mempair_load_extendsidi2" && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); } [(set_attr "move_type" "load") + (set_attr "type" "load") (set_attr "mode" "DI") (set_attr "length" "8")]) @@ -359,6 +365,7 @@ (define_insn "*th_mempair_load_zero_extendsidi2" && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); } [(set_attr "move_type" "load") + (set_attr "type" "load") (set_attr "mode" "DI") (set_attr "length" "8")])