From patchwork Thu Aug 31 08:20:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 1828157 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=UWpRLWJD; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RbvKb5XF9z1yhD for ; Thu, 31 Aug 2023 18:22:27 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C762C3882676 for ; Thu, 31 Aug 2023 08:22:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C762C3882676 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693470145; bh=Z6atURnho0REEwoNtn3UTcP5IM3Kk6qniL1DyxbVKdM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=UWpRLWJDkWPf3qAqysQb2tB3rhMrJHn1ooSOd1Ut8JOEPIQ58BqyjrJ4jAGKrPABO uGyjGMM0uedQkApb1vpCoI0tcWBfS3ncJHXSwTxT2f9p2BfJ4d3jnD71dM+tDdXacT sSPlQpICyBAdStlh3qe7d7wqacy1LIq7rYZqtaoU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 8720C3858414 for ; Thu, 31 Aug 2023 08:20:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8720C3858414 X-IronPort-AV: E=McAfee;i="6600,9927,10818"; a="462235634" X-IronPort-AV: E=Sophos;i="6.02,216,1688454000"; d="scan'208";a="462235634" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 01:20:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10818"; a="862938666" X-IronPort-AV: E=Sophos;i="6.02,216,1688454000"; d="scan'208";a="862938666" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 31 Aug 2023 01:20:29 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 883A4100512D; Thu, 31 Aug 2023 16:20:24 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH 05/13] [APX EGPR] Add register and memory constraints that disallow EGPR Date: Thu, 31 Aug 2023 16:20:16 +0800 Message-Id: <20230831082024.314097-6-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230831082024.314097-1-hongyu.wang@intel.com> References: <20230831082024.314097-1-hongyu.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hongyu Wang via Gcc-patches From: Hongyu Wang Reply-To: Hongyu Wang Cc: jakub@redhat.com, hongtao.liu@intel.com, hubicka@ucw.cz Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Kong Lingling For APX, as we extended the GENERAL_REG_CLASS, new constraints are needed to restrict insns that cannot adopt EGPR either in its reg or memory operands. gcc/ChangeLog: * config/i386/constraints.md (h): New register constraint for GENERAL_GPR16. (Bt): New non-EGPR memory constraint. (BT): Likewise for Bm constraint. * config/i386/i386.h (enum reg_class): Add new reg class GENERAL_GPR16. --- gcc/config/i386/constraints.md | 19 ++++++++++++++++++- gcc/config/i386/i386.h | 4 ++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index fd490f39110..f487bf2e5a3 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -19,7 +19,7 @@ ;;; Unused letters: ;;; H -;;; h j z +;;; j z ;; Integer register constraints. ;; It is not necessary to define 'r' here. @@ -165,6 +165,8 @@ (define_register_constraint "YW" ;; k TLS address that allows insn using non-integer registers ;; n Memory operand without REX prefix ;; r Broadcast memory operand +;; t Memory operand without EGPR +;; T Vector memory operand without EGPR ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. @@ -201,6 +203,18 @@ (define_special_memory_constraint "Bn" "@internal Memory operand without REX prefix." (match_operand 0 "norex_memory_operand")) +(define_memory_constraint "Bt" + "@internal Memory operand without GPR32." + (and (match_operand 0 "memory_operand") + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + +(define_special_memory_constraint "BT" + "@internal vector memory operand without GPR32." + (and (match_operand 0 "vector_memory_operand") + (not (and (match_test "TARGET_APX_EGPR") + (match_test "x86_extended_rex2reg_mentioned_p (op)"))))) + (define_special_memory_constraint "Br" "@internal bcst memory operand." (match_operand 0 "bcst_mem_operand")) @@ -371,3 +385,6 @@ (define_address_constraint "Tv" (define_address_constraint "Ts" "Address operand without segment register" (match_operand 0 "address_no_seg_operand")) + +(define_register_constraint "h" + "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS") diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 1ab291177f5..7ec3086641c 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1295,6 +1295,8 @@ enum reg_class %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */ + GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp + %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ FLOAT_REGS, SSE_FIRST_REG, @@ -1357,6 +1359,7 @@ enum reg_class "INDEX_REGS", \ "LEGACY_REGS", \ "GENERAL_REGS", \ + "GENERAL_GPR16", \ "FP_TOP_REG", "FP_SECOND_REG", \ "FLOAT_REGS", \ "SSE_FIRST_REG", \ @@ -1395,6 +1398,7 @@ enum reg_class { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \ + { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \ { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \