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Mon, 28 Aug 2023 12:04:35 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c21500b001bf574dd1fesm7727757pll.141.2023.08.28.12.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:04:35 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add Types to Un-Typed Vector Instructions: Date: Mon, 28 Aug 2023 12:03:15 -0700 Message-ID: <20230828190432.2530773-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/ This patch updates vector instructions to ensure that no insn is left without a type attribute. Creates a placeholder type "vector" for insns where a type isn't clear Tested for regressions using rv32/rv64 gc/gcv multilib with newlib/linux. gcc/Changelog: * config/riscv/autovec-vls.md: Update types * config/riscv/riscv.md: Add vector placeholder type * config/riscv/vector.md: Update types Signed-off-by: Edwin Lu --- gcc/config/riscv/autovec-vls.md | 15 ++++++++++++--- gcc/config/riscv/riscv.md | 3 ++- gcc/config/riscv/vector.md | 17 ++++++++++++----- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 1b1d940d779..35b86de25c7 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -68,6 +68,7 @@ (define_insn_and_split "*mov_mem_to_mem" } DONE; } + [(set_attr "type" "vmov")] ) (define_insn_and_split "*mov" @@ -89,6 +90,7 @@ (define_insn_and_split "*mov" gcc_assert (ok_p); DONE; } + [(set_attr "type" "vmov")] ) (define_expand "mov" @@ -130,7 +132,9 @@ (define_insn_and_split "*mov_lra" riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; -}) +} + [(set_attr "type" "vmov")] +) (define_insn "*mov_vls" [(set (match_operand:VLS 0 "register_operand" "=vr") @@ -157,6 +161,7 @@ (define_insn_and_split "@vec_duplicate" riscv_vector::RVV_UNOP, operands); DONE; } + [(set_attr "type" "vector")] ) ;; ------------------------------------------------------------------------- @@ -180,7 +185,9 @@ (define_insn_and_split "3" riscv_vector::emit_vlmax_insn (code_for_pred (, mode), riscv_vector::RVV_BINOP, operands); DONE; -}) +} +[(set_attr "type" "vector")] +) ;; ------------------------------------------------------------------------------- ;; ---- [INT] Unary operations @@ -201,4 +208,6 @@ (define_insn_and_split "2" insn_code icode = code_for_pred (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); DONE; -}) +} +[(set_attr "type" "vector")] +) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 47d14d99903..4d062307ad9 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -410,6 +410,7 @@ (define_attr "ext_enabled" "no,yes" ;; vgather vector register gather instructions ;; vcompress vector compress instruction ;; vmov whole vector register move +;; vector unknown vector instruction (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -429,7 +430,7 @@ (define_attr "type" vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov" + vgather,vcompress,vmov,vector" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index a442e0fdd3c..ea836968878 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -878,13 +878,15 @@ (define_insn "@vundefined" [(set (match_operand:V 0 "register_operand" "=vr") (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))] "TARGET_VECTOR" - "") + "" + [(set_attr "type" "vector")]) (define_insn "@vundefined" [(set (match_operand:VB 0 "register_operand" "=vr") (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))] "TARGET_VECTOR" - "") + "" + [(set_attr "type" "vector")]) (define_expand "@vreinterpret" [(set (match_operand:V 0 "register_operand") @@ -935,7 +937,8 @@ (define_insn "@vlmax_avl" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))] "TARGET_VECTOR" - "") + "" + [(set_attr "type" "vector")]) ;; Set VXRM (define_insn "vxrmsi" @@ -1135,7 +1138,9 @@ (define_insn_and_split "*mov_lra" riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; -}) +} +[(set_attr "type" "vector")] +) (define_insn_and_split "*mov_lra" [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr") @@ -1155,7 +1160,9 @@ (define_insn_and_split "*mov_lra" riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; -}) +} +[(set_attr "type" "vector")] +) ;; Define tuple modes data movement. ;; operands[2] is used to save the offset of each subpart.