From patchwork Wed Aug 2 01:13:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 1815702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=WKYrc+1M; dkim-atps=neutral Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RFvDZ5yZDz1yYC for ; Wed, 2 Aug 2023 11:15:41 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 81E11385843A for ; Wed, 2 Aug 2023 01:15:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 81E11385843A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690938939; bh=ePU2fTjCPPFcep0CZOs86JXWSjzEZwDVgm8x6+jNkJI=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=WKYrc+1MLp9t+hvGTSQloONOpIFnsDmhpZCAsHq1XB8jJzs3SESkl7B297euQj7dL x+aRI/8IEesTxAkSWu7aFJNq1Ly/xBe7HkNisLCl4vAqduhs04233paMSKTxpUqbJP bQV0QqvyK5i6dzKBEF6O5iBnr8G85dVqnPy3UyU4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 4106B3858D39 for ; Wed, 2 Aug 2023 01:15:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4106B3858D39 X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="368350660" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="368350660" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 18:15:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="722677516" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="722677516" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 01 Aug 2023 18:15:12 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 240E2100519F; Wed, 2 Aug 2023 09:15:12 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Support vec_fmaddsub/vec_fmsubadd for vector HFmode. Date: Wed, 2 Aug 2023 09:13:11 +0800 Message-Id: <20230802011311.771803-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Liu, Hongtao" Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" AVX512FP16 supports vfmaddsubXXXph and vfmsubaddXXXph. Also remove scalar mode from fmaddsub/fmsubadd pattern since there's no scalar instruction for that. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready to push to trunk. gcc/ChangeLog: PR target/81904 * config/i386/sse.md (vec_fmaddsub4): Extend to vector HFmode, use mode iterator VFH instead. (vec_fmsubadd4): Ditto. (fma_fmaddsub_): Remove scalar mode from iterator, use VFH_AVX512VL instead. (fma_fmsubadd_): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr81904.c: New test. --- gcc/config/i386/sse.md | 44 ++++++++++++------------- gcc/testsuite/gcc.target/i386/pr81904.c | 22 +++++++++++++ 2 files changed, 44 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr81904.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 51961bbfc0b..4e75c9addaa 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5803,21 +5803,21 @@ (define_insn "_fnmsub__mask3" ;; But this doesn't seem useful in practice. (define_expand "vec_fmaddsub4" - [(set (match_operand:VF 0 "register_operand") - (unspec:VF - [(match_operand:VF 1 "nonimmediate_operand") - (match_operand:VF 2 "nonimmediate_operand") - (match_operand:VF 3 "nonimmediate_operand")] + [(set (match_operand:VFH 0 "register_operand") + (unspec:VFH + [(match_operand:VFH 1 "nonimmediate_operand") + (match_operand:VFH 2 "nonimmediate_operand") + (match_operand:VFH 3 "nonimmediate_operand")] UNSPEC_FMADDSUB))] "TARGET_FMA || TARGET_FMA4 || ( == 64 || TARGET_AVX512VL)") (define_expand "vec_fmsubadd4" - [(set (match_operand:VF 0 "register_operand") - (unspec:VF - [(match_operand:VF 1 "nonimmediate_operand") - (match_operand:VF 2 "nonimmediate_operand") - (neg:VF - (match_operand:VF 3 "nonimmediate_operand"))] + [(set (match_operand:VFH 0 "register_operand") + (unspec:VFH + [(match_operand:VFH 1 "nonimmediate_operand") + (match_operand:VFH 2 "nonimmediate_operand") + (neg:VFH + (match_operand:VFH 3 "nonimmediate_operand"))] UNSPEC_FMADDSUB))] "TARGET_FMA || TARGET_FMA4 || ( == 64 || TARGET_AVX512VL)") @@ -5877,11 +5877,11 @@ (define_insn "*fma_fmaddsub_" (set_attr "mode" "")]) (define_insn "fma_fmaddsub_" - [(set (match_operand:VFH_SF_AVX512VL 0 "register_operand" "=v,v,v") - (unspec:VFH_SF_AVX512VL - [(match_operand:VFH_SF_AVX512VL 1 "" "%0,0,v") - (match_operand:VFH_SF_AVX512VL 2 "" ",v,") - (match_operand:VFH_SF_AVX512VL 3 "" "v,,0")] + [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v,v") + (unspec:VFH_AVX512VL + [(match_operand:VFH_AVX512VL 1 "" "%0,0,v") + (match_operand:VFH_AVX512VL 2 "" ",v,") + (match_operand:VFH_AVX512VL 3 "" "v,,0")] UNSPEC_FMADDSUB))] "TARGET_AVX512F && && " "@ @@ -5943,12 +5943,12 @@ (define_insn "*fma_fmsubadd_" (set_attr "mode" "")]) (define_insn "fma_fmsubadd_" - [(set (match_operand:VFH_SF_AVX512VL 0 "register_operand" "=v,v,v") - (unspec:VFH_SF_AVX512VL - [(match_operand:VFH_SF_AVX512VL 1 "" "%0,0,v") - (match_operand:VFH_SF_AVX512VL 2 "" ",v,") - (neg:VFH_SF_AVX512VL - (match_operand:VFH_SF_AVX512VL 3 "" "v,,0"))] + [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v,v") + (unspec:VFH_AVX512VL + [(match_operand:VFH_AVX512VL 1 "" "%0,0,v") + (match_operand:VFH_AVX512VL 2 "" ",v,") + (neg:VFH_AVX512VL + (match_operand:VFH_AVX512VL 3 "" "v,,0"))] UNSPEC_FMADDSUB))] "TARGET_AVX512F && && " "@ diff --git a/gcc/testsuite/gcc.target/i386/pr81904.c b/gcc/testsuite/gcc.target/i386/pr81904.c new file mode 100644 index 00000000000..9f5ad0bd952 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81904.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2 -mprefer-vector-width=512" } */ +/* { dg-final { scan-assembler-times "vfmaddsub...ph\[ \t\]+\[^\n\]*%zmm\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsubadd...ph\[ \t\]+\[^\n\]*%zmm\[0-9\]" 1 } } */ + +void vec_fmaddsub_fp16(int n, _Float16 da_r, _Float16 *x, _Float16* y, _Float16* __restrict z) +{ + for (int i = 0; i < 32; i += 2) + { + z[i] = da_r * x[i] - y[i]; + z[i+1] = da_r * x[i+1] + y[i+1]; + } +} + +void vec_fmasubadd_fp16(int n, _Float16 da_r, _Float16 *x, _Float16* y, _Float16* __restrict z) +{ + for (int i = 0; i < 32; i += 2) + { + z[i] = da_r * x[i] + y[i]; + z[i+1] = da_r * x[i+1] - y[i+1]; + } +}