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[98.210.197.24]) by smtp.gmail.com with ESMTPSA id n11-20020aa7904b000000b0066a613c4a58sm3277889pfo.102.2023.07.21.11.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 11:30:38 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org, Manolis Tsamis Cc: kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , gnu-toolchain@rivosinc.com, Philipp Tomsich , Vineet Gupta Subject: [PATCH v2] RISC-V: optim const DF +0.0 store to mem [PR/110748] Date: Fri, 21 Jul 2023 11:30:35 -0700 Message-Id: <20230721183035.2892020-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Fixes: ef85d150b5963 ("RISC-V: Enable TARGET_SUPPORTS_WIDE_INT") (gcc-13 regression) DF +0.0 is bitwise all zeros so int x0 store to mem can be used to optimize it. void zd(double *) { *d = 0.0; } currently: | fmv.d.x fa5,zero | fsd fa5,0(a0) | ret With patch | sd zero,0(a0) | ret This came to light when testing the in-flight f-m-o patch where an ICE was getting triggered due to lack of this pattern but turns out this is an independent optimization of its own [1] [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624857.html Ran thru full multilib testsuite, there was 1 false failure due to random string "lw" appearing in lto build assembler output, which is also fixed in the patch. gcc/Changelog: PR target/110748 * config/riscv/predicates.md (const_0_operand): Add back const_double. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr110748-1.c: New Test. * gcc.target/riscv/xtheadfmv-fmv.c: Add '\t' around test patterns to avoid random string matches. Signed-off-by: Vineet Gupta --- Changes since v1: - No code changes - Updated commitlog: typo, "Fixes:" tag, mention PR in Changelog entry --- gcc/config/riscv/predicates.md | 2 +- gcc/testsuite/gcc.target/riscv/pr110748-1.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 8 ++++---- 3 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr110748-1.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 5a22c77f0cd0..9db28c2def7e 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -58,7 +58,7 @@ (match_test "INTVAL (op) + 1 != 0"))) (define_predicate "const_0_operand" - (and (match_code "const_int,const_wide_int,const_vector") + (and (match_code "const_int,const_wide_int,const_double,const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) (define_predicate "const_1_operand" diff --git a/gcc/testsuite/gcc.target/riscv/pr110748-1.c b/gcc/testsuite/gcc.target/riscv/pr110748-1.c new file mode 100644 index 000000000000..2f5bc08aae72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr110748-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ +/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */ + + +void zd(double *d) { *d = 0.0; } +void zf(float *f) { *f = 0.0; } + +/* { dg-final { scan-assembler-not "\tfmv\\.d\\.x\t" } } */ +/* { dg-final { scan-assembler-not "\tfmv\\.s\\.x\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c index 1036044291e7..89eb48bed1b9 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c @@ -18,7 +18,7 @@ d2ll (double d) /* { dg-final { scan-assembler "th.fmv.hw.x" } } */ /* { dg-final { scan-assembler "fmv.x.w" } } */ /* { dg-final { scan-assembler "th.fmv.x.hw" } } */ -/* { dg-final { scan-assembler-not "sw" } } */ -/* { dg-final { scan-assembler-not "fld" } } */ -/* { dg-final { scan-assembler-not "fsd" } } */ -/* { dg-final { scan-assembler-not "lw" } } */ +/* { dg-final { scan-assembler-not "\tsw\t" } } */ +/* { dg-final { scan-assembler-not "\tfld\t" } } */ +/* { dg-final { scan-assembler-not "\tfsd\t" } } */ +/* { dg-final { scan-assembler-not "\tlw\t" } } */