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Thu, 18 May 2023 13:57:22 -0700 (PDT) Received: from vineet-framework.ba.rivosinc.com ([71.202.114.183]) by smtp.gmail.com with ESMTPSA id jj5-20020a170903048500b001ac82e8491csm1203644plb.282.2023.05.18.13.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 13:57:21 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , Christoph Mullner , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH] RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] Date: Thu, 18 May 2023 13:57:16 -0700 Message-Id: <20230518205716.3258223-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" [part #2 of PR/109279] SPEC2017 deepsjeng uses large constants which currently generates less than ideal code. This fix improves codegen for large constants which have same low and hi parts: e.g. long long f(void) { return 0x0101010101010101ull; } Before li a5,0x1010000 addi a5,a5,0x101 mv a0,a5 slli a5,a5,32 add a0,a5,a0 ret With patch li a5,0x1010000 addi a5,a5,0x101 slli a0,a5,32 add a0,a0,a5 ret This is testsuite clean. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_split_integer): if loval is equal to hival, ASHIFT the corresponding regs. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.cc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 79122699b6f5..4e1bb2f14cf8 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -703,13 +703,18 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); - riscv_move_integer (hi, hi, hival, mode); riscv_move_integer (lo, lo, loval, mode); - hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); - hi = force_reg (mode, hi); + if (loval == hival) + hi = gen_rtx_ASHIFT (mode, lo, GEN_INT (32)); + else + { + riscv_move_integer (hi, hi, hival, mode); + hi = gen_rtx_ASHIFT (mode, hi, GEN_INT (32)); + } - return gen_rtx_fmt_ee (PLUS, mode, hi, lo); + hi = force_reg (mode, hi); + return gen_rtx_PLUS (mode, hi, lo); } /* Return true if X is a thread-local symbol. */