From patchwork Fri May 12 02:24:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1780357 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=TAE5VEpf; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client 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12 May 2023 02:24:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 924E3385694E X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="353812627" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="353812627" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 19:24:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="677494462" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="677494462" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga006.jf.intel.com with ESMTP; 11 May 2023 19:24:35 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id C4F121010211; Fri, 12 May 2023 10:24:34 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: Pan Li , Juzhe Zhong Subject: [committed] RISC-V: Fix RVV binary auto-vectorizaiton test fails Date: Fri, 12 May 2023 10:24:32 +0800 Message-Id: <20230512022432.207773-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Pan Li In rv32: FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vand-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vrem-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmul-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vand-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vdiv-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vor-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-scalar-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmax-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vor-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) In rv64: FAIL: gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) Signed-off-by: Juzhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-run.c: Fix fail. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Ditto. --- gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c | 2 +- 22 files changed, 23 insertions(+), 23 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c index 67e9f8ca242..159478c6947 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c index aba9c842b1d..d9109fd8774 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c index 1e801743cf9..a8ecf9767e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c index aabd2e03231..82a5fe23e7d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c index d9ba5a385b9..64c2eeec7cf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c index 1c7def563ac..c13755ed06a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c index 3cd766b95a3..67f37c1e170 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c index c8f4ce88f65..aa9a3c55abe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c index 40fdfbd8922..7d9b75ae0b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c index 90e5c971150..cf184e24b1e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c index 03496305901..9bbaf763157 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c index 34f9348498b..b461f8ba484 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c index ff1d0bbf32e..07278b22b2d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c index 19e38ca8ff1..e8441c0605b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c index a21bae4708f..f436b8a82a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c index e5eb1c48f73..5401e8d3ecd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c index d364871fd4f..ae115a2f503 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c index db3bee3c49a..4a4c064e101 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c index 68dbdcf021a..5b6961d1f63 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c index 26867a0bbd7..f7a2691b9f3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c @@ -1,5 +1,5 @@ -/* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c index 68b9648738f..ab0975a6408 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c index 3e5885eb659..9729ad14eb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ #include "vxor-template.h"