diff mbox series

[committed] RISC-V: prefetch.* only take base register with zero-offset for the address

Message ID 20230220153645.115207-1-kito.cheng@sifive.com
State New
Headers show
Series [committed] RISC-V: prefetch.* only take base register with zero-offset for the address | expand

Commit Message

Kito Cheng Feb. 20, 2023, 3:36 p.m. UTC 
Catched by running gcc.c-torture/execute/builtin-prefetch-2.c with
-march=rv64gc_zicbop.

gcc/ChangeLog:

	* config/riscv/riscv.md (prefetch): Use r instead of p for the
	address operand.
	(riscv_prefetchi_<mode>): Ditto.
---
 gcc/config/riscv/riscv.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 487059ebe97..a5507fadc2d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3066,7 +3066,7 @@  (define_insn "riscv_zero_<mode>"
 )
 
 (define_insn "prefetch"
-  [(prefetch (match_operand 0 "address_operand" "p")
+  [(prefetch (match_operand 0 "address_operand" "r")
              (match_operand 1 "imm5_operand" "i")
              (match_operand 2 "const_int_operand" "n"))]
   "TARGET_ZICBOP"
@@ -3080,7 +3080,7 @@  (define_insn "prefetch"
 })
 
 (define_insn "riscv_prefetchi_<mode>"
-  [(unspec_volatile:X [(match_operand:X 0 "address_operand" "p")
+  [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
               (match_operand:X 1 "imm5_operand" "i")]
               UNSPECV_PREI)]
   "TARGET_ZICBOP"