RISC-V: Add VSETVL testcases for indexed loads/stores.

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test.
        * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test.

---
 .../riscv/rvv/vsetvl/avl_single-72.c          | 27 +++++++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-76.c          | 24 +++++++++++++++++
 .../riscv/rvv/vsetvl/avl_single-77.c          | 27 +++++++++++++++++++
 3 files changed, 78 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c

committed, thanks!

On Sun, Jan 29, 2023 at 11:35 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
>         * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test.
>         * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test.
>
> ---
>  .../riscv/rvv/vsetvl/avl_single-72.c          | 27 +++++++++++++++++++
>  .../riscv/rvv/vsetvl/avl_single-76.c          | 24 +++++++++++++++++
>  .../riscv/rvv/vsetvl/avl_single-77.c          | 27 +++++++++++++++++++
>  3 files changed, 78 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
> new file mode 100644
> index 00000000000..b1e28abd4fe
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n, int cond)
> +{
> +  size_t vl = 101;
> +  for (size_t i = 0; i < n; i++)
> +    {
> +      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> +      __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> +      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
> +      __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
> +    }
> +
> +  for (size_t i = 0; i < n; i++)
> +    {
> +      vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl);
> +      vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2 (in + i + 200, index, vl);
> +      __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl);
> +    }
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
> new file mode 100644
> index 00000000000..1b6e818d209
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
> @@ -0,0 +1,24 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n, int cond)
> +{
> +  size_t vl = 101;
> +  for (size_t i = 0; i < n; i++)
> +    {
> +      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> +      __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +    }
> +
> +  for (size_t i = 0; i < n; i++)
> +    {
> +      vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl);
> +      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 600, vl);
> +      __riscv_vsoxei8_v_f32mf2 (out + i + 200, index, v, vl);
> +    }
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
> new file mode 100644
> index 00000000000..9fb16052385
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n, int cond)
> +{
> +  size_t vl = 101;
> +  for (size_t i = 0; i < n; i++)
> +    {
> +      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> +      __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +    }
> +
> +  for (size_t i = 0; i < n; i++)
> +    {
> +      vbool64_t mask = __riscv_vlm_v_b64 (in + 10000, vl);
> +      vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl);
> +      vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 30000, vl);
> +      vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in + i + 200, index, vl);
> +      __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl);
> +    }
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +
> --
> 2.36.3
>