diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
new file mode 100644
index 00000000000..cd4ee7dd0d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, 5);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, 5);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, 5);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, 5);
+    __riscv_vse8_v_i8mf8 (out + 700, v, 5);
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, 5);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, 5);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
new file mode 100644
index 00000000000..cdb2c8f948e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t vl, size_t m, size_t n, size_t a, size_t b) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, 4);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v0, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, 4);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, 4);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, 4);
+              }
+            }
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, 4);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
new file mode 100644
index 00000000000..ba2d57ea570
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t vl, size_t m, size_t n, size_t a, size_t b) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, 4);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, 4);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, 4);
+              }
+            }
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v0, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, 4);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, 4);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
new file mode 100644
index 00000000000..ced6cb8c408
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t vl, size_t m, size_t n, size_t a, size_t b) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, 4);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, 4);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, 4);
+              }
+            }
+          }
+        } else {
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
new file mode 100644
index 00000000000..fd75172a89a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, 
+size_t vl, size_t m, size_t n, size_t a, size_t b) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            for (size_t i_a = 0; i_a < a; i_a++){
+              for (size_t i_b = 0; i_b < b; i_b++){
+                vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, 4);
+                vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, 4);
+                __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, 4);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
new file mode 100644
index 00000000000..76ec7ae14ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int n2)
+{
+  for (int i = 0 ; i < n2; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 800 + i, 9);
+    __riscv_vse8_v_i8mf8 (out + 800 + i, v, 9);
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900 + i, 5);
+    __riscv_vse8_v_i8mf8 (out + 900 + i, v, 5);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*9,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
new file mode 100644
index 00000000000..3da7b8722c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m) {
+  vbool64_t mask = *(vbool64_t*)mask_in;
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, 4);
+      vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, 4);
+      __riscv_vse8_v_i8mf8 (out + i, v1, 4);
+    } else {
+      vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i, 4);
+      vint16mf4_t v1 = __riscv_vle16_v_i16mf4_mu(mask, v0, base + i + 100, 4);
+      __riscv_vse16_v_i16mf4 (out + i, v1, 4);
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
new file mode 100644
index 00000000000..2a9616eb7ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
+  vbool64_t mask = *(vbool64_t*)mask_in;
+
+  for (size_t i = 0; i < m; i++) {
+    for (size_t j = 0; j < n; j++){
+      if ((i + j) % 2 == 0) {
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j, 4);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 100, 4);
+        __riscv_vse8_v_i8mf8 (out + i + j, v1, 4);
+      } else {
+        vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j, 4);
+        vint16mf4_t v1 = __riscv_vle16_v_i16mf4_mu(mask, v0, base + i + j + 100, 4);
+        __riscv_vse16_v_i16mf4 (out + i + j, v1, 4);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
new file mode 100644
index 00000000000..21be9c08250
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 700, 4);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 700, 4);
+        __riscv_vse8_v_i8mf8 (out + i + j + 700, v1, 4);
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 500, 4);
+          __riscv_vse8_v_i8mf8 (out + i + j + 500, v0, 4);
+        } else {
+          vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j + 600, 4);
+          __riscv_vse16_v_i16mf4 (out + i + j + 600, v0, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 200, 4);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 300, 4);
+        __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, 4);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
new file mode 100644
index 00000000000..92d830ce638
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 500, 4);
+          __riscv_vse8_v_i8mf8 (out + i + j + 500, v0, 4);
+        } else {
+          vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j + 600, 4);
+          __riscv_vse16_v_i16mf4 (out + i + j + 600, v0, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 200, 4);
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 300, 4);
+        __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, 4);
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
new file mode 100644
index 00000000000..550c3a38eb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200, 4);
+          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 200, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v1, 4);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300, 4);
+          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 300, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v1, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < n; j++){
+        vint8mf8_t v1 = __riscv_vle8_v_i8mf8(base + i + j + 300, 4);
+        __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, 4);
+      }
+    }
+  }
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
new file mode 100644
index 00000000000..667effa8ba5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, 4);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v0, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j, 4);
+            vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j, 4);
+            __riscv_vse8_v_i8mf8 (out + i + 600, v1, 4);
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, 4);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
new file mode 100644
index 00000000000..3b486df4fe5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
+
+  for (size_t i = 0; i < m; i++) {
+    if (i % 2 == 0) {
+      for (size_t j = 0; j < n; j++){
+        if (j % 2 == 0) {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 200, v0, 4);
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300 + j, 4);
+          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 300 + j, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 300, v1, 4);
+        }
+      }
+    } else {
+      for (size_t j = 0; j < vl; j++){
+        if (j % 2 == 0) {
+          for (size_t k = 0; k < n; k++) {
+            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j, 4);
+            __riscv_vse8_v_i8mf8 (out + i + 600, v0, 4);
+          }
+        } else {
+          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 700, 4);
+          __riscv_vse8_v_i8mf8 (out + i + 800, v0, 4);
+        }
+      }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
new file mode 100644
index 00000000000..331ebab6e3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, size_t n, size_t cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 100, 17);
+        __riscv_vse8_v_i8mf8 (out + i + 100, v, 17);
+      } else {
+        vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 200, 4);
+        __riscv_vse32_v_i32m1 (out + i + 200, v, 4);
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
new file mode 100644
index 00000000000..3ed73ea32b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, size_t n, size_t cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i == cond) {
+        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 100, 17);
+        __riscv_vse8_v_i8mf8 (out + i + 100, v, 17);
+      } else {
+        vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + 200, 4);
+        __riscv_vse32_v_i32m1 (out + i + 200, v, 4);
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
new file mode 100644
index 00000000000..1f7c0f036a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, 5);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, 5);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, 5);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, 5);
+    __riscv_vse8_v_i8mf8 (out + 700, v, 5);
+  }
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + 900 + i);
+    *(vint8mf8_t*) (out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
new file mode 100644
index 00000000000..f24e129b4dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, 5);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, 5);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, 5);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, 5);
+    __riscv_vse8_v_i8mf8 (out + 700, v, 5);
+  }
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + 900 + i);
+    *(vint8mf8_t*) (out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 1000 + i, 19);
+    __riscv_vse32_v_i32m1 (out + 1000 + i, v, 19);
+  }
+
+  for (int i = 0 ; i < n * n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 2000 + i, 8);
+    __riscv_vse32_v_i32m1 (out + 2000 + i, v, 8);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
new file mode 100644
index 00000000000..02bc648cc34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
@@ -0,0 +1,45 @@
+#include "riscv_vector.h"
+
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (n > cond) {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, 5);
+    vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, 5);
+    __riscv_vse8_v_i8mf8 (out + 600, v2, 5);
+  } else {
+    vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, 5);
+    __riscv_vse8_v_i8mf8 (out + 700, v, 5);
+  }
+
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + 900 + i);
+    *(vint8mf8_t*) (out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 1000 + i, 19);
+    __riscv_vse32_v_i32m1 (out + 1000 + i, v, 19);
+  }
+
+  for (int i = 0 ; i < n * n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + 2000 + i, 8);
+    __riscv_vse32_v_i32m1 (out + 2000 + i, v, 8);
+  }
+
+  for (int i = 0 ; i < n * n * n; i++) {
+    vint16mf2_t v = __riscv_vle16_v_i16mf2 (in + 3000 + i, 8);
+    __riscv_vse16_v_i16mf2 (out + 3000 + i, v, 8);
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
new file mode 100644
index 00000000000..618adb78577
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
@@ -0,0 +1,195 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f2 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8mf8_t v = __riscv_vle8_v_u8mf8 (in + i + j, 17);
+          __riscv_vse8_v_u8mf8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f3 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf4_t v = __riscv_vle8_v_i8mf4 (in + i + j, 17);
+          __riscv_vse8_v_i8mf4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f4 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8mf4_t v = __riscv_vle8_v_u8mf4 (in + i + j, 17);
+          __riscv_vse8_v_u8mf4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f5 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf2_t v = __riscv_vle8_v_i8mf2 (in + i + j, 17);
+          __riscv_vse8_v_i8mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f6 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8mf2_t v = __riscv_vle8_v_u8mf2 (in + i + j, 17);
+          __riscv_vse8_v_u8mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f7 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8m1_t v = __riscv_vle8_v_i8m1 (in + i + j, 17);
+          __riscv_vse8_v_i8m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f8 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8m1_t v = __riscv_vle8_v_u8m1 (in + i + j, 17);
+          __riscv_vse8_v_u8m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f9 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8m2_t v = __riscv_vle8_v_i8m2 (in + i + j, 17);
+          __riscv_vse8_v_i8m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f10 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8m2_t v = __riscv_vle8_v_u8m2 (in + i + j, 17);
+          __riscv_vse8_v_u8m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f11 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8m4_t v = __riscv_vle8_v_i8m4 (in + i + j, 17);
+          __riscv_vse8_v_i8m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f12 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8m4_t v = __riscv_vle8_v_u8m4 (in + i + j, 17);
+          __riscv_vse8_v_u8m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f13 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8m8_t v = __riscv_vle8_v_i8m8 (in + i + j, 17);
+          __riscv_vse8_v_i8m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f14 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint8m8_t v = __riscv_vle8_v_u8m8 (in + i + j, 17);
+          __riscv_vse8_v_u8m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 14 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
new file mode 100644
index 00000000000..c9d4950e7d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
+          vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in + i + j + 16, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+void f2 (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool8_t mask = *(vbool8_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
+          __riscv_vse64_v_f64m8 (out + i + j, v, 17);
+          vfloat64m8_t v2 = __riscv_vle64_v_f64m8_m (mask, in + i + j + 16, 17);
+          __riscv_vse64_v_f64m8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
new file mode 100644
index 00000000000..2e8647ed4bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
+          vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + j + 16, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+void f2 (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool8_t mask = *(vbool8_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
+          __riscv_vse64_v_f64m8 (out + i + j, v, 17);
+          vfloat64m8_t v2 = __riscv_vle64_v_f64m8_tumu (mask, v, in + i + j + 16, 17);
+          __riscv_vse64_v_f64m8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
new file mode 100644
index 00000000000..c1af8fcf637
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v = __riscv_vle8_v_i8mf8(in + 100, 4);
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8(in + 1, 4);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4(in + 2, 4);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2(in + 3, 4);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2(in + 4, 4);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 4);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 4);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 4);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 4);
+  
+  for (int i = 0; i < n; i++)
+    {
+      v = __riscv_vle8_v_i8mf8_tu(v, in + i + 5, 4);
+      __riscv_vse8_v_i8mf8 (out + i + 5, v, 4);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
new file mode 100644
index 00000000000..9abcc0f6343
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int n)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8(in + 1, 4);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4(in + 2, 4);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2(in + 3, 4);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2(in + 4, 4);
+  vint16mf4_t v = __riscv_vle16_v_i16mf4(in + 100, 4);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 4);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 4);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 4);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 4);
+  
+  for (int i = 0; i < n; i++)
+    {
+      v = __riscv_vle16_v_i16mf4_tum(mask, v, in + i + 5, 4);
+      __riscv_vse16_v_i16mf4_m (mask, out + i + 5, v, 4);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\),\s*v0.t} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e16,\s*mf4,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
new file mode 100644
index 00000000000..c9171247420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int n)
+{
+  vbool32_t mask = *(vbool32_t*)mask_in;
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8(in + 1, 4);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4(in + 2, 4);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2(in + 3, 4);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2(in + 4, 4);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 4);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 4);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 4);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 4);
+
+  vint16mf2_t v = __riscv_vle16_v_i16mf2(in + 100, 4);
+  
+  for (int i = 0; i < n; i++)
+    {
+      v = __riscv_vle16_v_i16mf2_tumu(mask, v, in + i + 5, 4);
+      __riscv_vse16_v_i16mf2_m (mask, out + i + 5, v, 4);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\),\s*v0.t} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e16,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
new file mode 100644
index 00000000000..6256e2e59e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int n)
+{
+  vbool32_t mask = *(vbool32_t*)mask_in;
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8(in + 1, 4);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4(in + 2, 4);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2(in + 3, 4);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2(in + 4, 4);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 4);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 4);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 4);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 4);
+
+  vint16mf2_t v = __riscv_vle16_v_i16mf2(in + 100, 4);
+  
+  for (int i = 0; i < n; i++)
+    {
+      v = __riscv_vle16_v_i16mf2_mu(mask, v, in + i + 5, 4);
+      __riscv_vse16_v_i16mf2_m (mask, out + i + 5, v, 4);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\),\s*v0.t} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e16,\s*mf2,\s*t[au],\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
new file mode 100644
index 00000000000..b936d72704e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int n)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8(in + 1, 4);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4(in + 2, 4);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2(in + 3, 4);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2(in + 4, 4);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 4);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 4);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 4);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 4);
+
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = __riscv_vle16_v_u16mf4_m(mask, in + i + 5, 4);
+      __riscv_vse16_v_u16mf4_m (mask, out + i + 5, v, 4);
+    }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\),\s*v0.t} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
new file mode 100644
index 00000000000..fcf0a8c4aeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      vint8mf2_t v = __riscv_vle8_v_i8mf2 (in + i*10 + j*10, 8);
+      __riscv_vse8_v_i8mf2 (out + i*10 + j*10, v, 8);
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + k, v, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
new file mode 100644
index 00000000000..32f33948d7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
@@ -0,0 +1,168 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f3 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint16mf4_t v = __riscv_vle16_v_i16mf4 (in + i + j, 17);
+          __riscv_vse16_v_i16mf4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f4 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint16mf4_t v = __riscv_vle16_v_u16mf4 (in + i + j, 17);
+          __riscv_vse16_v_u16mf4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f5 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint16mf2_t v = __riscv_vle16_v_i16mf2 (in + i + j, 17);
+          __riscv_vse16_v_i16mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f6 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint16mf2_t v = __riscv_vle16_v_u16mf2 (in + i + j, 17);
+          __riscv_vse16_v_u16mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f7 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint16m1_t v = __riscv_vle16_v_i16m1 (in + i + j, 17);
+          __riscv_vse16_v_i16m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f8 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint16m1_t v = __riscv_vle16_v_u16m1 (in + i + j, 17);
+          __riscv_vse16_v_u16m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f9 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint16m2_t v = __riscv_vle16_v_i16m2 (in + i + j, 17);
+          __riscv_vse16_v_i16m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f10 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint16m2_t v = __riscv_vle16_v_u16m2 (in + i + j, 17);
+          __riscv_vse16_v_u16m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f11 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint16m4_t v = __riscv_vle16_v_i16m4 (in + i + j, 17);
+          __riscv_vse16_v_i16m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f12 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint16m4_t v = __riscv_vle16_v_u16m4 (in + i + j, 17);
+          __riscv_vse16_v_u16m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f13 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint16m8_t v = __riscv_vle16_v_i16m8 (in + i + j, 17);
+          __riscv_vse16_v_i16m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f14 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint16m8_t v = __riscv_vle16_v_u16m8 (in + i + j, 17);
+          __riscv_vse16_v_u16m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 12 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e16,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
new file mode 100644
index 00000000000..4d08475271e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
@@ -0,0 +1,141 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f5 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint32mf2_t v = __riscv_vle32_v_i32mf2 (in + i + j, 17);
+          __riscv_vse32_v_i32mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f6 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint32mf2_t v = __riscv_vle32_v_u32mf2 (in + i + j, 17);
+          __riscv_vse32_v_u32mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f7 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint32m1_t v = __riscv_vle32_v_i32m1 (in + i + j, 17);
+          __riscv_vse32_v_i32m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f8 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint32m1_t v = __riscv_vle32_v_u32m1 (in + i + j, 17);
+          __riscv_vse32_v_u32m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f9 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint32m2_t v = __riscv_vle32_v_i32m2 (in + i + j, 17);
+          __riscv_vse32_v_i32m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f10 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint32m2_t v = __riscv_vle32_v_u32m2 (in + i + j, 17);
+          __riscv_vse32_v_u32m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f11 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint32m4_t v = __riscv_vle32_v_i32m4 (in + i + j, 17);
+          __riscv_vse32_v_i32m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f12 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint32m4_t v = __riscv_vle32_v_u32m4 (in + i + j, 17);
+          __riscv_vse32_v_u32m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f13 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint32m8_t v = __riscv_vle32_v_i32m8 (in + i + j, 17);
+          __riscv_vse32_v_i32m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f14 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint32m8_t v = __riscv_vle32_v_u32m8 (in + i + j, 17);
+          __riscv_vse32_v_u32m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 10 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
new file mode 100644
index 00000000000..976d38958d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
@@ -0,0 +1,77 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f5 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + j, 17);
+          __riscv_vse32_v_f32mf2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f7 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat32m1_t v = __riscv_vle32_v_f32m1 (in + i + j, 17);
+          __riscv_vse32_v_f32m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f9 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat32m2_t v = __riscv_vle32_v_f32m2 (in + i + j, 17);
+          __riscv_vse32_v_f32m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f11 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat32m4_t v = __riscv_vle32_v_f32m4 (in + i + j, 17);
+          __riscv_vse32_v_f32m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f13 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat32m8_t v = __riscv_vle32_v_f32m8 (in + i + j, 17);
+          __riscv_vse32_v_f32m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
new file mode 100644
index 00000000000..defeb86d774
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
@@ -0,0 +1,114 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f7 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + j, 17);
+          __riscv_vse64_v_i64m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f8 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + j, 17);
+          __riscv_vse64_v_u64m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f9 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint64m2_t v = __riscv_vle64_v_i64m2 (in + i + j, 17);
+          __riscv_vse64_v_i64m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f10 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint64m2_t v = __riscv_vle64_v_u64m2 (in + i + j, 17);
+          __riscv_vse64_v_u64m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f11 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint64m4_t v = __riscv_vle64_v_i64m4 (in + i + j, 17);
+          __riscv_vse64_v_i64m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f12 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint64m4_t v = __riscv_vle64_v_u64m4 (in + i + j, 17);
+          __riscv_vse64_v_u64m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f13 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint64m8_t v = __riscv_vle64_v_i64m8 (in + i + j, 17);
+          __riscv_vse64_v_i64m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f14 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vuint64m8_t v = __riscv_vle64_v_u64m8 (in + i + j, 17);
+          __riscv_vse64_v_u64m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 8 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
new file mode 100644
index 00000000000..1ae8a034ea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+
+void f8 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m1_t v = __riscv_vle64_v_f64m1 (in + i + j, 17);
+          __riscv_vse64_v_f64m1 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f9 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m2_t v = __riscv_vle64_v_f64m2 (in + i + j, 17);
+          __riscv_vse64_v_f64m2 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f11 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m4_t v = __riscv_vle64_v_f64m4 (in + i + j, 17);
+          __riscv_vse64_v_f64m4 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+void f13 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
+          __riscv_vse64_v_f64m8 (out + i + j, v, 17);
+        }
+    }
+  }
+}
+
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
new file mode 100644
index 00000000000..ac943abeaf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
+          vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + j + 16, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+void f2 (void * restrict in, void * restrict out, int l, int n, int m)
+{
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
+          __riscv_vse64_v_f64m8 (out + i + j, v, 17);
+          vfloat64m8_t v2 = __riscv_vle64_v_f64m8_tu (v, in + i + j + 16, 17);
+          __riscv_vse64_v_f64m8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
new file mode 100644
index 00000000000..731930ef9e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
+          vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + j + 16, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + 16, v2, 17);
+          vint8mf8_t v3 = __riscv_vle8_v_i8mf8_mu (mask, v2, in + i + j + 16, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + 16, v3, 17);
+        }
+    }
+  }
+}
+
+void f2 (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool8_t mask = *(vbool8_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
+          __riscv_vse64_v_f64m8 (out + i + j, v, 17);
+          vfloat64m8_t v2 = __riscv_vle64_v_f64m8_tu (v, in + i + j + 16, 17);
+          __riscv_vse64_v_f64m8 (out + i + j + 16, v2, 17);
+          vfloat64m8_t v3 = __riscv_vle64_v_f64m8_mu (mask, v2, in + i + j + 16, 17);
+          __riscv_vse64_v_f64m8 (out + i + j + 16, v3, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
new file mode 100644
index 00000000000..2dfca074bf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
+          vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tum (mask, v, in + i + j + 16, 17);
+          __riscv_vse8_v_i8mf8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+void f2 (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
+{
+  vbool8_t mask = *(vbool8_t*)mask_in;
+  for (int i = 0; i < l; i++){
+    for (int j = 0; j < m; j++){
+      for (int k = 0; k < n; k++)
+        {
+          vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
+          __riscv_vse64_v_f64m8 (out + i + j, v, 17);
+          vfloat64m8_t v2 = __riscv_vle64_v_f64m8_tum (mask, v, in + i + j + 16, 17);
+          __riscv_vse64_v_f64m8 (out + i + j + 16, v2, 17);
+        }
+    }
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
new file mode 100644
index 00000000000..b084eea5403
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + 10000, 19);
+  __riscv_vse32_v_f32mf2 (out + 10000, v, 19);
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v1 = __riscv_vle16_v_i16mf2 (in + i + 1, 19);
+      __riscv_vse16_v_i16mf2 (out + i + 1, v1, 19);
+      asm volatile ("":::"memory");
+      vint32mf2_t v2 = __riscv_vle32_v_i32mf2 (in + i + 2, 19);
+      __riscv_vse32_v_i32mf2 (out + i + 2, v2, 19);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
new file mode 100644
index 00000000000..2e58f088d6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int n)
+{
+  vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + 10000, 19);
+  __riscv_vse32_v_f32mf2 (out + 10000, v, 19);
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v1 = __riscv_vle16_v_i16mf2 (in + i + 1, 19);
+      __riscv_vse16_v_i16mf2 (out + i + 1, v1, 19);
+      vint32mf2_t v2 = __riscv_vle32_v_i32mf2 (in + i + 2, 19);
+      __riscv_vse32_v_i32mf2 (out + i + 2, v2, 19);
+      vbool64_t mask = *(vbool64_t*)mask_in;
+      vint32mf2_t v3 = __riscv_vle32_v_i32mf2_tumu (mask, v2, in + i + 200, 13);
+      *(vint32mf2_t*)(out + i + 200) = v3;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*13,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*19,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
new file mode 100644
index 00000000000..a751700b2a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
@@ -0,0 +1,189 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, void * restrict mask_in, int n)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v_8mf8_0 = __riscv_vle8_v_i8mf8 ((int8_t *)(in + i), 0);
+      __riscv_vse8_v_i8mf8 ((int8_t *)(out + i), v_8mf8_0, 0);
+
+      vint8mf8_t v_8mf8_0_tu = __riscv_vle8_v_i8mf8_tu (v_8mf8_0, (int8_t *)(in + i + 1), 0);
+      __riscv_vse8_v_i8mf8_m (mask, (int8_t *)(out + i + 1), v_8mf8_0_tu, 0);
+
+      vint8mf8_t v_8mf8_0_mu = __riscv_vle8_v_i8mf8_mu (mask, v_8mf8_0, (int8_t *)(in + i + 2), 0);
+      __riscv_vse8_v_i8mf8 ((int8_t *)(out + i + 2), v_8mf8_0_tu, 0);
+
+      vint8mf8_t v_8mf8_1 = __riscv_vle8_v_i8mf8 ((int8_t *)(in + i + 3), 7);
+      __riscv_vse8_v_i8mf8 ((int8_t *)(out + i + 3), v_8mf8_1, 7);
+      
+      vint8mf8_t v_8mf8_2 = __riscv_vle8_v_i8mf8 ((int8_t *)(in + i + 4), 17);
+      __riscv_vse8_v_i8mf8 ((int8_t *)(out + i + 4), v_8mf8_2, 17);
+
+      vint8mf8_t v_8mf8_3 = __riscv_vle8_v_i8mf8 ((int8_t *)(in + i + 5), 27);
+      __riscv_vse8_v_i8mf8 ((int8_t *)(out + i + 5), v_8mf8_3, 27);
+
+      vint8mf4_t v_8mf4_1 = __riscv_vle8_v_i8mf4 ((int8_t *)(in + i + 6), 7);
+      __riscv_vse8_v_i8mf4 ((int8_t *)(out + i + 6), v_8mf4_1, 7);
+      
+      vint8mf4_t v_8mf4_2 = __riscv_vle8_v_i8mf4 ((int8_t *)(in + i + 7), 17);
+      __riscv_vse8_v_i8mf4 ((int8_t *)(out + i + 7), v_8mf4_2, 17);
+
+      vint8mf4_t v_8mf4_3 = __riscv_vle8_v_i8mf4 ((int8_t *)(in + i + 8), 27);
+      __riscv_vse8_v_i8mf4 ((int8_t *)(out + i + 8), v_8mf4_3, 27);
+
+      vint8mf2_t v_8mf2_1 = __riscv_vle8_v_i8mf2 ((int8_t *)(in + i + 9), 7);
+      __riscv_vse8_v_i8mf2 ((int8_t *)(out + i + 9), v_8mf2_1, 7);
+      
+      vint8mf2_t v_8mf2_2 = __riscv_vle8_v_i8mf2 ((int8_t *)(in + i + 10), 17);
+      __riscv_vse8_v_i8mf2 ((int8_t *)(out + i + 10), v_8mf2_2, 17);
+
+      vint8mf2_t v_8mf2_3 = __riscv_vle8_v_i8mf2 ((int8_t *)(in + i + 11), 27);
+      __riscv_vse8_v_i8mf2 ((int8_t *)(out + i + 11), v_8mf2_3, 27);
+
+      vint8m1_t v_8m1_1 = __riscv_vle8_v_i8m1 ((int8_t *)(in + i + 12), 7);
+      __riscv_vse8_v_i8m1 ((int8_t *)(out + i + 12), v_8m1_1, 7);
+      
+      vint8m1_t v_8m1_2 = __riscv_vle8_v_i8m1 ((int8_t *)(in + i + 13), 17);
+      __riscv_vse8_v_i8m1 ((int8_t *)(out + i + 13), v_8m1_2, 17);
+
+      vint8m1_t v_8m1_3 = __riscv_vle8_v_i8m1 ((int8_t *)(in + i + 14), 27);
+      __riscv_vse8_v_i8m1 ((int8_t *)(out + i + 14), v_8m1_3, 27);
+
+      vint8m2_t v_8m2_1 = __riscv_vle8_v_i8m2 ((int8_t *)(in + i + 15), 7);
+      __riscv_vse8_v_i8m2 ((int8_t *)(out + i + 15), v_8m2_1, 7);
+      
+      vint8m2_t v_8m2_2 = __riscv_vle8_v_i8m2 ((int8_t *)(in + i + 16), 17);
+      __riscv_vse8_v_i8m2 ((int8_t *)(out + i + 16), v_8m2_2, 17);
+
+      vint8m2_t v_8m2_3 = __riscv_vle8_v_i8m2 ((int8_t *)(in + i + 17), 27);
+      __riscv_vse8_v_i8m2 ((int8_t *)(out + i + 17), v_8m2_3, 27);
+
+      vint8m4_t v_8m4_1 = __riscv_vle8_v_i8m4 ((int8_t *)(in + i + 18), 7);
+      __riscv_vse8_v_i8m4 ((int8_t *)(out + i + 18), v_8m4_1, 7);
+      
+      vint8m4_t v_8m4_2 = __riscv_vle8_v_i8m4 ((int8_t *)(in + i + 19), 17);
+      __riscv_vse8_v_i8m4 ((int8_t *)(out + i + 19), v_8m4_2, 17);
+
+      vint8m4_t v_8m4_3 = __riscv_vle8_v_i8m4 ((int8_t *)(in + i + 20), 27);
+      __riscv_vse8_v_i8m4 ((int8_t *)(out + i + 20), v_8m4_3, 27);
+
+      vint8m8_t v_8m8_1 = __riscv_vle8_v_i8m8 ((int8_t *)(in + i + 21), 7);
+      __riscv_vse8_v_i8m8 ((int8_t *)(out + i + 21), v_8m8_1, 7);
+      
+      vint8m8_t v_8m8_2 = __riscv_vle8_v_i8m8 ((int8_t *)(in + i + 22), 17);
+      __riscv_vse8_v_i8m8 ((int8_t *)(out + i + 22), v_8m8_2, 17);
+
+      vint8m8_t v_8m8_3 = __riscv_vle8_v_i8m8 ((int8_t *)(in + i + 23), 27);
+      __riscv_vse8_v_i8m8 ((int8_t *)(out + i + 23), v_8m8_3, 27);
+
+      vuint16mf4_t v_16mf4_1 = *(vuint16mf4_t*)(in + 24 + i);
+      *(vuint16mf4_t*)(out + 24 + i) = v_16mf4_1;
+      
+      vuint16mf2_t v_16mf2_1 = *(vuint16mf2_t*)(in + 25 + i);
+      *(vuint16mf2_t*)(out + 25 + i) = v_16mf2_1;
+
+      vuint32mf2_t v_32mf2_t = *(vuint32mf2_t*)(in + 26 + i);
+      *(vuint32mf2_t*)(out + 26 + i) = v_32mf2_t;
+
+      vuint8mf2_t v_8mf2_4 = *(vuint8mf2_t*)(in + 27 + i);
+      *(vuint8mf2_t*)(out + 27 + i) = v_8mf2_4;
+
+      vuint8mf4_t v_8mf4_4 = *(vuint8mf4_t*)(in + 28 + i);
+      *(vuint8mf4_t*)(out + 28 + i) = v_8mf4_4;
+
+      vint32mf2_t v_32mf2_1 = __riscv_vle32_v_i32mf2 ((int32_t *)(in + i + 49), 7);
+      __riscv_vse32_v_i32mf2 ((int32_t *)(out + i + 49), v_32mf2_1, 7);
+      
+      vint32mf2_t v_32mf2_2 = __riscv_vle32_v_i32mf2 ((int32_t *)(in + i + 30), 17);
+      __riscv_vse32_v_i32mf2 ((int32_t *)(out + i + 30), v_32mf2_2, 17);
+
+      vint32mf2_t v_32mf2_3 = __riscv_vle32_v_i32mf2 ((int32_t *)(in + i + 31), 27);
+      __riscv_vse32_v_i32mf2 ((int32_t *)(out + i + 31), v_32mf2_3, 27);
+
+      vint32m1_t v_32m1_1 = __riscv_vle32_v_i32m1 ((int32_t *)(in + i + 32), 7);
+      __riscv_vse32_v_i32m1 ((int32_t *)(out + i + 32), v_32m1_1, 7);
+      
+      vint32m1_t v_32m1_2 = __riscv_vle32_v_i32m1 ((int32_t *)(in + i + 33), 17);
+      __riscv_vse32_v_i32m1 ((int32_t *)(out + i + 33), v_32m1_2, 17);
+
+      vint32m1_t v_32m1_3 = __riscv_vle32_v_i32m1 ((int32_t *)(in + i + 34), 27);
+      __riscv_vse32_v_i32m1 ((int32_t *)(out + i + 34), v_32m1_3, 27);
+
+      vint32m2_t v_32m2_1 = __riscv_vle32_v_i32m2 ((int32_t *)(in + i + 35), 7);
+      __riscv_vse32_v_i32m2 ((int32_t *)(out + i + 35), v_32m2_1, 7);
+      
+      vint32m2_t v_32m2_2 = __riscv_vle32_v_i32m2 ((int32_t *)(in + i + 36), 17);
+      __riscv_vse32_v_i32m2 ((int32_t *)(out + i + 36), v_32m2_2, 17);
+
+      vint32m2_t v_32m2_3 = __riscv_vle32_v_i32m2 ((int32_t *)(in + i + 37), 27);
+      __riscv_vse32_v_i32m2 ((int32_t *)(out + i + 37), v_32m2_3, 27);
+
+      vint32m4_t v_32m4_1 = __riscv_vle32_v_i32m4 ((int32_t *)(in + i + 38), 7);
+      __riscv_vse32_v_i32m4 ((int32_t *)(out + i + 38), v_32m4_1, 7);
+      
+      vint32m4_t v_32m4_2 = __riscv_vle32_v_i32m4 ((int32_t *)(in + i + 39), 17);
+      __riscv_vse32_v_i32m4 ((int32_t *)(out + i + 39), v_32m4_2, 17);
+
+      vint32m4_t v_32m4_3 = __riscv_vle32_v_i32m4 ((int32_t *)(in + i + 40), 27);
+      __riscv_vse32_v_i32m4 ((int32_t *)(out + i + 40), v_32m4_3, 27);
+
+      vint32m8_t v_32m8_1 = __riscv_vle32_v_i32m8 ((int32_t *)(in + i + 41), 7);
+      __riscv_vse32_v_i32m8 ((int32_t *)(out + i + 41), v_32m8_1, 7);
+      
+      vint32m8_t v_32m8_2 = __riscv_vle32_v_i32m8 ((int32_t *)(in + i + 42), 17);
+      __riscv_vse32_v_i32m8 ((int32_t *)(out + i + 42), v_32m8_2, 17);
+
+      vint32m8_t v_32m8_3 = __riscv_vle32_v_i32m8 ((int32_t *)(in + i + 43), 27);
+      __riscv_vse32_v_i32m8 ((int32_t *)(out + i + 43), v_32m8_3, 27);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*7,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*27,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 6 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 37 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
new file mode 100644
index 00000000000..b8aac96f9bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
+
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8_tu (v1, in + i + 5, 5);
+      __riscv_vse8_v_i8mf8 (out + i + 5, v, 5);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
new file mode 100644
index 00000000000..702326cdf86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
+
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = __riscv_vle16_v_i16mf4 (in + i + 5, 7);
+      __riscv_vse16_v_i16mf4 (out + i + 5, v, 7);
+      fn3 ();
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vsetivli\s+zero,\s*7,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
new file mode 100644
index 00000000000..cd776dad7a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
+
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = __riscv_vle16_v_i16mf4 (in + i + 5, 5);
+      __riscv_vse16_v_i16mf4 (out + i + 5, v, 5);
+      fn3 ();
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vsetivli\s+zero,\s*5,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
new file mode 100644
index 00000000000..6795a1ef4bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
+
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = __riscv_vle16_v_i16mf4 (in + i + 5, 5);
+      __riscv_vse16_v_i16mf4 (out + i + 5, v, 5);
+      vint16mf2_t v2 = __riscv_vle16_v_i16mf2 (in + i + 6, 8);
+      __riscv_vse16_v_i16mf2 (out + i + 6, v2, 8);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vsetivli\s+zero,\s*5,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
new file mode 100644
index 00000000000..a4c8de7b067
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int * restrict out2, int n)
+{
+  vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
+  vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
+  vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
+  vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
+  
+  __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
+  __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
+  __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
+  __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
+
+  for (int i = 0 ; i < n * n; i++)
+    out2[i] = out2[i] + out2[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out2[i] = out2[i] * out2[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out2[i] = out2[i] * out2[i];
+
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = __riscv_vle8_v_i8mf8_tu (v1, in + i + 5, 5);
+      __riscv_vse8_v_i8mf8 (out + i + 5, v, 5);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
new file mode 100644
index 00000000000..149f01b4d5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict mask_in, int n, int cond)
+{
+  vbool64_t mask = *(vbool64_t*)mask_in;
+  vfloat32mf2_t vf32mf2 = *(vfloat32mf2_t*)in;
+  vint16mf4_t vf16mf4 = *(vint16mf4_t*)(in + 5);
+  asm volatile ("":::"memory");
+  vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + 10000, 5);
+  __riscv_vse32_v_f32mf2 (out + 10000, v, 5);
+
+  if (cond)
+    {
+      vfloat32mf2_t vt = __riscv_vle32_v_f32mf2_tumu (mask, vf32mf2, in + 20000, 5);
+      __riscv_vse32_v_f32mf2 (out + 20000, vt, 5);
+    }
+  else
+    {
+      vint16mf4_t vt = __riscv_vle16_v_i16mf4_tumu (mask, vf16mf4, in + 20000, 5);
+      __riscv_vse16_v_i16mf4 (out + 20000, vt, 5);
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v0 = __riscv_vle32_v_f32mf2_tu (v, in + i + 100, 5);
+      vint16mf2_t v1 = __riscv_vle16_v_i16mf2 (in + i + 200, 6);
+      vint8mf2_t v2 = __riscv_vle8_v_i8mf2 (in + i + 300, 7);
+      vint8mf4_t v3 = __riscv_vle8_v_i8mf4 (in + i + 400, 8);
+      vint8mf8_t v4 = __riscv_vle8_v_i8mf8 (in + i + 500, 9);
+      vint32mf2_t v5 = __riscv_vle32_v_i32mf2 (in + i + 600, 5);
+      
+      __riscv_vse32_v_f32mf2 (out + i + 100, v0, 5);
+      __riscv_vse16_v_i16mf2 (out + i + 200, v1, 6);
+      __riscv_vse8_v_i8mf2 (out + i + 300, v2, 7);
+      __riscv_vse8_v_i8mf4 (out + i + 400, v3, 8);
+      __riscv_vse8_v_i8mf8 (out + i + 500, v4, 9);
+      __riscv_vse32_v_i32mf2 (out + i + 600, v5, 5);
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e16,\s*mf4,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e32,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
