From patchwork Mon Dec 19 15:06:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1717417 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=u26s54qQ; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NbNN70jhvz1ydd for ; Tue, 20 Dec 2022 02:07:03 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 14B713858288 for ; Mon, 19 Dec 2022 15:07:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 14B713858288 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671462421; bh=tYwL+eiaAjXwYgQ6SsVMRRwnd+1w3WHOV+8QZfRx7zY=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=u26s54qQLYN0AQkuw0Zse/KEC17lxWqNQGs1iINA6/CueuSN5KBga9J83wkhVTdqv s0bVKxFMSmO7poNG+B80FZvWXBbMncgrayfODANEhXJXN0u2QCYkLUfeG90966kB2W EPfGuRVQT6VFEcsEQhnbHYW0/ktsahn2cILjDvjA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 5E26038582A3 for ; Mon, 19 Dec 2022 15:06:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5E26038582A3 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E08E4AD7; Mon, 19 Dec 2022 07:07:21 -0800 (PST) Received: from e126323.arm.com (unknown [10.57.11.95]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80B3C3F71A; Mon, 19 Dec 2022 07:06:40 -0800 (PST) To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed] arm: correctly define __ARM_FEATURE_CLZ Date: Mon, 19 Dec 2022 15:06:26 +0000 Message-Id: <20221219150626.2972660-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-16.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The ACLE requires that __ARM_FEATURE_CLZ be defined if the hardware supports it; it's also clear that this doesn't mean the current ISA, so we must define this even when compiling for Thumb1 if the target supports CLZ in A32. This brings GCC into alignment with Clang. gcc/ChangeLog: * config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of preprocessor macro when target has CLZ in another ISA. --- gcc/config/arm/arm-c.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc index 86c56bf2680..202898fa041 100644 --- a/gcc/config/arm/arm-c.cc +++ b/gcc/config/arm/arm-c.cc @@ -238,8 +238,12 @@ arm_cpu_builtins (struct cpp_reader* pfile) builtin_define_with_int_value ("__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); + /* ACLE says that __ARM_FEATURE_CLZ is defined if the hardware + supports it; it's also clear that this doesn't mean the current + ISA, so we define this even when compiling for Thumb1 if the + target supports CLZ in A32. */ def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ", - ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) + ((TARGET_ARM_ARCH >= 5 && arm_arch_notm) || TARGET_ARM_ARCH_ISA_THUMB >=2)); def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",