diff mbox series

RISC-V: Fix annotation

Message ID 20221214083902.169785-1-juzhe.zhong@rivai.ai
State New
Headers show
Series RISC-V: Fix annotation | expand

Commit Message

钟居哲 Dec. 14, 2022, 8:39 a.m. UTC
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc: Fix annotation.

---
 gcc/config/riscv/riscv-vsetvl.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jeff Law Dec. 16, 2022, 7:53 p.m. UTC | #1
On 12/14/22 01:39, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vsetvl.cc: Fix annotation.
Just roll this into the patch that adds riscv-vsetvl.cc.

jeff
Kito Cheng Dec. 19, 2022, 3:07 p.m. UTC | #2
Merged into previou patch.

Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org> 於 2022年12月17日 週六 03:54
寫道:

>
>
> On 12/14/22 01:39, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > gcc/ChangeLog:
> >
> >          * config/riscv/riscv-vsetvl.cc: Fix annotation.
> Just roll this into the patch that adds riscv-vsetvl.cc.
>
> jeff
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index c602426b542..3ca3fc15e5a 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -35,7 +35,7 @@  along with GCC; see the file COPYING3.  If not see
 
     -  Each avl operand is either an immediate (must be in range 0 ~ 31) or reg.
 
-    This pass consists of 3 phases:
+    This pass consists of 5 phases:
 
     -  Phase 1 - compute VL/VTYPE demanded information within each block
        by backward data-flow analysis.