diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 25e09f41d73..2ed29e22606 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -42,6 +42,8 @@ dg-init
 set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
 	"" $CFLAGS
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
+	"" $CFLAGS
 
 # All done.
 dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
new file mode 100644
index 00000000000..fb4edb459a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v2;
+      *(vuint16mf4_t*)(out + i + 1000) = v2;
+      vbool32_t v4;
+      *(vbool32_t*)(out + i + 3000) = v4;
+      vbool16_t v5;
+      *(vbool16_t*)(out + i + 4000) = v5;
+      vbool8_t v6;
+      *(vbool8_t*)(out + i + 5000) = v6;
+      vbool4_t v7;
+      *(vbool4_t*)(out + i + 6000) = v7;
+      vbool2_t v8;
+      *(vbool2_t*)(out + i + 7000) = v8;
+      vbool1_t v9;
+      *(vbool1_t*)(out + i + 8000) = v9;
+      vuint32mf2_t v10;
+      *(vuint32mf2_t*)(out + i + 100000) = v10;
+    }
+  
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1 = *(vint8mf8_t*)(in + i + 100000);
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
new file mode 100644
index 00000000000..016af8fc67b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
@@ -0,0 +1,154 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo1 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vbool64_t v2 = *(vbool64_t*)(in + 2);
+  vbool64_t v3 = *(vbool64_t*)(in + 3);
+  vbool64_t v4 = *(vbool64_t*)(in + 4);
+  vbool64_t v5 = *(vbool64_t*)(in + 5);
+  vbool64_t v6 = *(vbool64_t*)(in + 6);
+  vbool64_t v7 = *(vbool64_t*)(in + 7);
+  vbool64_t v8 = *(vbool64_t*)(in + 8);
+  *(vbool64_t*)(out + 1) = v1;
+  *(vbool64_t*)(out + 2) = v2;
+  *(vbool64_t*)(out + 3) = v3;
+  *(vbool64_t*)(out + 4) = v4;
+  *(vbool64_t*)(out + 5) = v5;
+  *(vbool64_t*)(out + 6) = v6;
+  *(vbool64_t*)(out + 7) = v7;
+  *(vbool64_t*)(out + 8) = v8;
+}
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vbool32_t v2 = *(vbool32_t*)(in + 2);
+  vbool32_t v3 = *(vbool32_t*)(in + 3);
+  vbool32_t v4 = *(vbool32_t*)(in + 4);
+  vbool32_t v5 = *(vbool32_t*)(in + 5);
+  vbool32_t v6 = *(vbool32_t*)(in + 6);
+  vbool32_t v7 = *(vbool32_t*)(in + 7);
+  vbool32_t v8 = *(vbool32_t*)(in + 8);
+  *(vbool32_t*)(out + 1) = v1;
+  *(vbool32_t*)(out + 2) = v2;
+  *(vbool32_t*)(out + 3) = v3;
+  *(vbool32_t*)(out + 4) = v4;
+  *(vbool32_t*)(out + 5) = v5;
+  *(vbool32_t*)(out + 6) = v6;
+  *(vbool32_t*)(out + 7) = v7;
+  *(vbool32_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vbool16_t v2 = *(vbool16_t*)(in + 2);
+  vbool16_t v3 = *(vbool16_t*)(in + 3);
+  vbool16_t v4 = *(vbool16_t*)(in + 4);
+  vbool16_t v5 = *(vbool16_t*)(in + 5);
+  vbool16_t v6 = *(vbool16_t*)(in + 6);
+  vbool16_t v7 = *(vbool16_t*)(in + 7);
+  vbool16_t v8 = *(vbool16_t*)(in + 8);
+  *(vbool16_t*)(out + 1) = v1;
+  *(vbool16_t*)(out + 2) = v2;
+  *(vbool16_t*)(out + 3) = v3;
+  *(vbool16_t*)(out + 4) = v4;
+  *(vbool16_t*)(out + 5) = v5;
+  *(vbool16_t*)(out + 6) = v6;
+  *(vbool16_t*)(out + 7) = v7;
+  *(vbool16_t*)(out + 8) = v8;
+}
+
+void foo4 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vbool8_t v2 = *(vbool8_t*)(in + 2);
+  vbool8_t v3 = *(vbool8_t*)(in + 3);
+  vbool8_t v4 = *(vbool8_t*)(in + 4);
+  vbool8_t v5 = *(vbool8_t*)(in + 5);
+  vbool8_t v6 = *(vbool8_t*)(in + 6);
+  vbool8_t v7 = *(vbool8_t*)(in + 7);
+  vbool8_t v8 = *(vbool8_t*)(in + 8);
+  *(vbool8_t*)(out + 1) = v1;
+  *(vbool8_t*)(out + 2) = v2;
+  *(vbool8_t*)(out + 3) = v3;
+  *(vbool8_t*)(out + 4) = v4;
+  *(vbool8_t*)(out + 5) = v5;
+  *(vbool8_t*)(out + 6) = v6;
+  *(vbool8_t*)(out + 7) = v7;
+  *(vbool8_t*)(out + 8) = v8;
+}
+
+void foo5 (void * restrict in, void * restrict out)
+{
+  vbool4_t v1 = *(vbool4_t*)(in + 1);
+  vbool4_t v2 = *(vbool4_t*)(in + 2);
+  vbool4_t v3 = *(vbool4_t*)(in + 3);
+  vbool4_t v4 = *(vbool4_t*)(in + 4);
+  vbool4_t v5 = *(vbool4_t*)(in + 5);
+  vbool4_t v6 = *(vbool4_t*)(in + 6);
+  vbool4_t v7 = *(vbool4_t*)(in + 7);
+  vbool4_t v8 = *(vbool4_t*)(in + 8);
+  *(vbool4_t*)(out + 1) = v1;
+  *(vbool4_t*)(out + 2) = v2;
+  *(vbool4_t*)(out + 3) = v3;
+  *(vbool4_t*)(out + 4) = v4;
+  *(vbool4_t*)(out + 5) = v5;
+  *(vbool4_t*)(out + 6) = v6;
+  *(vbool4_t*)(out + 7) = v7;
+  *(vbool4_t*)(out + 8) = v8;
+}
+
+void foo6 (void * restrict in, void * restrict out)
+{
+  vbool2_t v1 = *(vbool2_t*)(in + 1);
+  vbool2_t v2 = *(vbool2_t*)(in + 2);
+  vbool2_t v3 = *(vbool2_t*)(in + 3);
+  vbool2_t v4 = *(vbool2_t*)(in + 4);
+  vbool2_t v5 = *(vbool2_t*)(in + 5);
+  vbool2_t v6 = *(vbool2_t*)(in + 6);
+  vbool2_t v7 = *(vbool2_t*)(in + 7);
+  vbool2_t v8 = *(vbool2_t*)(in + 8);
+  *(vbool2_t*)(out + 1) = v1;
+  *(vbool2_t*)(out + 2) = v2;
+  *(vbool2_t*)(out + 3) = v3;
+  *(vbool2_t*)(out + 4) = v4;
+  *(vbool2_t*)(out + 5) = v5;
+  *(vbool2_t*)(out + 6) = v6;
+  *(vbool2_t*)(out + 7) = v7;
+  *(vbool2_t*)(out + 8) = v8;
+}
+
+void foo7 (void * restrict in, void * restrict out)
+{
+  vbool1_t v1 = *(vbool1_t*)(in + 1);
+  vbool1_t v2 = *(vbool1_t*)(in + 2);
+  vbool1_t v3 = *(vbool1_t*)(in + 3);
+  vbool1_t v4 = *(vbool1_t*)(in + 4);
+  vbool1_t v5 = *(vbool1_t*)(in + 5);
+  vbool1_t v6 = *(vbool1_t*)(in + 6);
+  vbool1_t v7 = *(vbool1_t*)(in + 7);
+  vbool1_t v8 = *(vbool1_t*)(in + 8);
+  *(vbool1_t*)(out + 1) = v1;
+  *(vbool1_t*)(out + 2) = v2;
+  *(vbool1_t*)(out + 3) = v3;
+  *(vbool1_t*)(out + 4) = v4;
+  *(vbool1_t*)(out + 5) = v5;
+  *(vbool1_t*)(out + 6) = v6;
+  *(vbool1_t*)(out + 7) = v7;
+  *(vbool1_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
new file mode 100644
index 00000000000..185db998df1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
@@ -0,0 +1,143 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint8mf8_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint32mf2_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint64m1_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint8mf4_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint8mf4_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint32m1_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint32m1_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint64m2_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint64m2_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vint8mf2_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vint8mf2_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vint32m2_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vint32m2_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vint64m4_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vint64m4_t*)(out + 2) = v2;
+}
+
+void f10 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vint8m1_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vint8m1_t*)(out + 2) = v2;
+}
+
+void f11 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vint32m4_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vint32m4_t*)(out + 2) = v2;
+}
+
+void f12 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vint64m8_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vint64m8_t*)(out + 2) = v2;
+}
+
+void f13 (void * restrict in, void * restrict out)
+{
+  vint16m4_t v1 = *(vint16m4_t*)(in + 1);
+  vint8m2_t v2;
+  *(vint16m4_t*)(out + 1) = v1;
+  *(vint8m2_t*)(out + 2) = v2;
+}
+
+void f14 (void * restrict in, void * restrict out)
+{
+  vint16m4_t v1 = *(vint16m4_t*)(in + 1);
+  vint32m8_t v2;
+  *(vint16m4_t*)(out + 1) = v1;
+  *(vint32m8_t*)(out + 2) = v2;
+}
+
+void f15 (void * restrict in, void * restrict out)
+{
+  vint16m8_t v1 = *(vint16m8_t*)(in + 1);
+  vint8m4_t v2;
+  *(vint16m8_t*)(out + 1) = v1;
+  *(vint8m4_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
new file mode 100644
index 00000000000..95746b763e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint8mf8_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint64m1_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
new file mode 100644
index 00000000000..d3442457861
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
@@ -0,0 +1,92 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vfloat32mf2_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vfloat32mf2_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vfloat32m1_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vfloat32m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vfloat64m2_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vfloat64m2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vfloat32m2_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vfloat32m2_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vfloat64m4_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vfloat64m4_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vfloat32m4_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vfloat32m4_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vfloat64m8_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vfloat64m8_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint8m2_t v1 = *(vint8m2_t*)(in + 1);
+  vfloat32m8_t v2;
+  *(vint8m2_t*)(out + 1) = v1;
+  *(vfloat32m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
new file mode 100644
index 00000000000..9ed1020af29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
@@ -0,0 +1,89 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vfloat32mf2_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vfloat32mf2_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vfloat32m1_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vfloat32m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vfloat64m2_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vfloat64m2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vfloat32m2_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vfloat32m2_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vfloat64m4_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vfloat64m4_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vfloat32m4_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vfloat32m4_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vfloat64m8_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vfloat64m8_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint16m4_t v1 = *(vint16m4_t*)(in + 1);
+  vfloat32m8_t v2;
+  *(vint16m4_t*)(out + 1) = v1;
+  *(vfloat32m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
new file mode 100644
index 00000000000..f5d91c68a16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
new file mode 100644
index 00000000000..3d9e8370cc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vint8mf8_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vint64m1_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
new file mode 100644
index 00000000000..6ee416088ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
@@ -0,0 +1,147 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vbool64_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vint32mf2_t v2;
+  *(vbool64_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vint64m1_t v2;
+  *(vbool64_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vint16mf2_t v2;
+  *(vbool32_t*)(out + 1) = v1;
+  *(vint16mf2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vint32m1_t v2;
+  *(vbool32_t*)(out + 1) = v1;
+  *(vint32m1_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vint64m2_t v2;
+  *(vbool32_t*)(out + 1) = v1;
+  *(vint64m2_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vint16m1_t v2;
+  *(vbool16_t*)(out + 1) = v1;
+  *(vint16m1_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vint32m2_t v2;
+  *(vbool16_t*)(out + 1) = v1;
+  *(vint32m2_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vint64m4_t v2;
+  *(vbool16_t*)(out + 1) = v1;
+  *(vint64m4_t*)(out + 2) = v2;
+}
+
+void f10 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vint16m2_t v2;
+  *(vbool8_t*)(out + 1) = v1;
+  *(vint16m2_t*)(out + 2) = v2;
+}
+
+void f11 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vint32m4_t v2;
+  *(vbool8_t*)(out + 1) = v1;
+  *(vint32m4_t*)(out + 2) = v2;
+}
+
+void f12 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vint64m8_t v2;
+  *(vbool8_t*)(out + 1) = v1;
+  *(vint64m8_t*)(out + 2) = v2;
+}
+
+void f13 (void * restrict in, void * restrict out)
+{
+  vbool4_t v1 = *(vbool4_t*)(in + 1);
+  vint16m4_t v2;
+  *(vbool4_t*)(out + 1) = v1;
+  *(vint16m4_t*)(out + 2) = v2;
+}
+
+void f14 (void * restrict in, void * restrict out)
+{
+  vbool4_t v1 = *(vbool4_t*)(in + 1);
+  vint32m8_t v2;
+  *(vbool4_t*)(out + 1) = v1;
+  *(vint32m8_t*)(out + 2) = v2;
+}
+
+void f15 (void * restrict in, void * restrict out)
+{
+  vbool2_t v1 = *(vbool2_t*)(in + 1);
+  vint16m8_t v2;
+  *(vbool2_t*)(out + 1) = v1;
+  *(vint16m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
new file mode 100644
index 00000000000..7fba5560f88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void foo7 (void * restrict in, void * restrict out)
+{
+  vbool1_t v1 = *(vbool1_t*)(in + 1);
+  vbool2_t v2 = *(vbool2_t*)(in + 2);
+  vbool4_t v3 = *(vbool4_t*)(in + 3);
+  vbool8_t v4 = *(vbool8_t*)(in + 4);
+  vbool16_t v5 = *(vbool16_t*)(in + 5);
+  vbool32_t v6 = *(vbool32_t*)(in + 6);
+  vbool64_t v7 = *(vbool64_t*)(in + 7);
+  *(vbool1_t*)(out + 1) = v1;
+  *(vbool2_t*)(out + 2) = v2;
+  *(vbool4_t*)(out + 3) = v3;
+  *(vbool8_t*)(out + 4) = v4;
+  *(vbool16_t*)(out + 5) = v5;
+  *(vbool32_t*)(out + 6) = v6;
+  *(vbool64_t*)(out + 7) = v7;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 7 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 7 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
new file mode 100644
index 00000000000..01ea59db736
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  vint8mf4_t v5 = *(vint8mf4_t*)(in + 5);
+  vint16mf2_t v6 = *(vint16mf2_t*)(in + 6);
+  
+  vint8mf2_t v7 = *(vint8mf2_t*)(in + 7);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  *(vint8mf4_t*)(out + 5) = v5;
+  *(vint16mf2_t*)(out + 6) = v6;
+  
+  *(vint8mf2_t*)(out + 7) = v7;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
new file mode 100644
index 00000000000..431ec82846b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -0,0 +1,105 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  
+  vint8mf8_t v3 = *(vint8mf8_t*)(in + 3);
+  vint32mf2_t v4;
+  *(vint8mf8_t*)(out + 3) = v3;
+  *(vint32mf2_t*)(out + 4) = v4;
+  
+  vint8mf8_t v5 = *(vint8mf8_t*)(in + 5);
+  vint64m1_t v6;
+  *(vint8mf8_t*)(out + 5) = v5;
+  *(vint64m1_t*)(out + 6) = v6;
+  
+  vint8mf4_t v7 = *(vint8mf4_t*)(in + 7);
+  vint16mf2_t v8;
+  *(vint8mf4_t*)(out + 7) = v7;
+  *(vint16mf2_t*)(out + 8) = v8;
+  
+  vint8mf4_t v9 = *(vint8mf4_t*)(in + 9);
+  vint32m1_t v10;
+  *(vint8mf4_t*)(out + 9) = v9;
+  *(vint32m1_t*)(out + 10) = v10;
+  
+  vint8mf4_t v11 = *(vint8mf4_t*)(in + 11);
+  vint64m2_t v12;
+  *(vint8mf4_t*)(out + 11) = v11;
+  *(vint64m2_t*)(out + 12) = v12;
+  
+  vint8mf2_t v13 = *(vint8mf2_t*)(in + 13);
+  vint16m1_t v14;
+  *(vint8mf2_t*)(out + 13) = v13;
+  *(vint16m1_t*)(out + 14) = v14;
+  
+  vint8mf2_t v15 = *(vint8mf2_t*)(in + 15);
+  vint32m2_t v16;
+  *(vint8mf2_t*)(out + 15) = v15;
+  *(vint32m2_t*)(out + 16) = v16;
+  
+  vint8mf2_t v17 = *(vint8mf2_t*)(in + 17);
+  vint64m4_t v18;
+  *(vint8mf2_t*)(out + 17) = v17;
+  *(vint64m4_t*)(out + 18) = v18;
+  
+  vint8m1_t v19 = *(vint8m1_t*)(in + 19);
+  vint16m2_t v20;
+  *(vint8m1_t*)(out + 19) = v19;
+  *(vint16m2_t*)(out + 20) = v20;
+  
+  vint8m1_t v21 = *(vint8m1_t*)(in + 20);
+  vint32m4_t v22;
+  *(vint8m1_t*)(out + 20) = v21;
+  *(vint32m4_t*)(out + 21) = v22;
+  
+  vint8m1_t v23 = *(vint8m1_t*)(in + 23);
+  vint64m8_t v24;
+  *(vint8m1_t*)(out + 21) = v23;
+  *(vint64m8_t*)(out + 22) = v24;
+  
+  vint8m2_t v25 = *(vint8m2_t*)(in + 25);
+  vint16m4_t v26;
+  *(vint8m2_t*)(out + 25) = v25;
+  *(vint16m4_t*)(out + 26) = v26;
+  
+  vint8m2_t v27 = *(vint8m2_t*)(in + 27);
+  vint32m8_t v28;
+  *(vint8m2_t*)(out + 27) = v27;
+  *(vint32m8_t*)(out + 28) = v28;
+  
+  vint8m4_t v29 = *(vint8m4_t*)(in + 29);
+  vint16m8_t v30;
+  *(vint8m4_t*)(out + 29) = v29;
+  *(vint16m8_t*)(out + 30) = v30;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
new file mode 100644
index 00000000000..1660ab7d8d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
@@ -0,0 +1,70 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo1 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint8mf8_t v2 = *(vint8mf8_t*)(in + 2);
+  vint8mf8_t v3 = *(vint8mf8_t*)(in + 3);
+  vint8mf8_t v4 = *(vint8mf8_t*)(in + 4);
+  vint8mf8_t v5 = *(vint8mf8_t*)(in + 5);
+  vint8mf8_t v6 = *(vint8mf8_t*)(in + 6);
+  vint8mf8_t v7 = *(vint8mf8_t*)(in + 7);
+  vint8mf8_t v8 = *(vint8mf8_t*)(in + 8);
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+  *(vint8mf8_t*)(out + 3) = v3;
+  *(vint8mf8_t*)(out + 4) = v4;
+  *(vint8mf8_t*)(out + 5) = v5;
+  *(vint8mf8_t*)(out + 6) = v6;
+  *(vint8mf8_t*)(out + 7) = v7;
+  *(vint8mf8_t*)(out + 8) = v8;
+}
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint8mf4_t v2 = *(vint8mf4_t*)(in + 2);
+  vint8mf4_t v3 = *(vint8mf4_t*)(in + 3);
+  vint8mf4_t v4 = *(vint8mf4_t*)(in + 4);
+  vint8mf4_t v5 = *(vint8mf4_t*)(in + 5);
+  vint8mf4_t v6 = *(vint8mf4_t*)(in + 6);
+  vint8mf4_t v7 = *(vint8mf4_t*)(in + 7);
+  vint8mf4_t v8 = *(vint8mf4_t*)(in + 8);
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint8mf4_t*)(out + 2) = v2;
+  *(vint8mf4_t*)(out + 3) = v3;
+  *(vint8mf4_t*)(out + 4) = v4;
+  *(vint8mf4_t*)(out + 5) = v5;
+  *(vint8mf4_t*)(out + 6) = v6;
+  *(vint8mf4_t*)(out + 7) = v7;
+  *(vint8mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint8mf2_t v2 = *(vint8mf2_t*)(in + 2);
+  vint8mf2_t v3 = *(vint8mf2_t*)(in + 3);
+  vint8mf2_t v4 = *(vint8mf2_t*)(in + 4);
+  vint8mf2_t v5 = *(vint8mf2_t*)(in + 5);
+  vint8mf2_t v6 = *(vint8mf2_t*)(in + 6);
+  vint8mf2_t v7 = *(vint8mf2_t*)(in + 7);
+  vint8mf2_t v8 = *(vint8mf2_t*)(in + 8);
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint8mf2_t*)(out + 2) = v2;
+  *(vint8mf2_t*)(out + 3) = v3;
+  *(vint8mf2_t*)(out + 4) = v4;
+  *(vint8mf2_t*)(out + 5) = v5;
+  *(vint8mf2_t*)(out + 6) = v6;
+  *(vint8mf2_t*)(out + 7) = v7;
+  *(vint8mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
new file mode 100644
index 00000000000..13c801fc33e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
@@ -0,0 +1,70 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo1 (void * restrict in, void * restrict out)
+{
+  vuint8mf8_t v1 = *(vuint8mf8_t*)(in + 1);
+  vuint8mf8_t v2 = *(vuint8mf8_t*)(in + 2);
+  vuint8mf8_t v3 = *(vuint8mf8_t*)(in + 3);
+  vuint8mf8_t v4 = *(vuint8mf8_t*)(in + 4);
+  vuint8mf8_t v5 = *(vuint8mf8_t*)(in + 5);
+  vuint8mf8_t v6 = *(vuint8mf8_t*)(in + 6);
+  vuint8mf8_t v7 = *(vuint8mf8_t*)(in + 7);
+  vuint8mf8_t v8 = *(vuint8mf8_t*)(in + 8);
+  *(vuint8mf8_t*)(out + 1) = v1;
+  *(vuint8mf8_t*)(out + 2) = v2;
+  *(vuint8mf8_t*)(out + 3) = v3;
+  *(vuint8mf8_t*)(out + 4) = v4;
+  *(vuint8mf8_t*)(out + 5) = v5;
+  *(vuint8mf8_t*)(out + 6) = v6;
+  *(vuint8mf8_t*)(out + 7) = v7;
+  *(vuint8mf8_t*)(out + 8) = v8;
+}
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vuint8mf4_t v1 = *(vuint8mf4_t*)(in + 1);
+  vuint8mf4_t v2 = *(vuint8mf4_t*)(in + 2);
+  vuint8mf4_t v3 = *(vuint8mf4_t*)(in + 3);
+  vuint8mf4_t v4 = *(vuint8mf4_t*)(in + 4);
+  vuint8mf4_t v5 = *(vuint8mf4_t*)(in + 5);
+  vuint8mf4_t v6 = *(vuint8mf4_t*)(in + 6);
+  vuint8mf4_t v7 = *(vuint8mf4_t*)(in + 7);
+  vuint8mf4_t v8 = *(vuint8mf4_t*)(in + 8);
+  *(vuint8mf4_t*)(out + 1) = v1;
+  *(vuint8mf4_t*)(out + 2) = v2;
+  *(vuint8mf4_t*)(out + 3) = v3;
+  *(vuint8mf4_t*)(out + 4) = v4;
+  *(vuint8mf4_t*)(out + 5) = v5;
+  *(vuint8mf4_t*)(out + 6) = v6;
+  *(vuint8mf4_t*)(out + 7) = v7;
+  *(vuint8mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vuint8mf2_t v1 = *(vuint8mf2_t*)(in + 1);
+  vuint8mf2_t v2 = *(vuint8mf2_t*)(in + 2);
+  vuint8mf2_t v3 = *(vuint8mf2_t*)(in + 3);
+  vuint8mf2_t v4 = *(vuint8mf2_t*)(in + 4);
+  vuint8mf2_t v5 = *(vuint8mf2_t*)(in + 5);
+  vuint8mf2_t v6 = *(vuint8mf2_t*)(in + 6);
+  vuint8mf2_t v7 = *(vuint8mf2_t*)(in + 7);
+  vuint8mf2_t v8 = *(vuint8mf2_t*)(in + 8);
+  *(vuint8mf2_t*)(out + 1) = v1;
+  *(vuint8mf2_t*)(out + 2) = v2;
+  *(vuint8mf2_t*)(out + 3) = v3;
+  *(vuint8mf2_t*)(out + 4) = v4;
+  *(vuint8mf2_t*)(out + 5) = v5;
+  *(vuint8mf2_t*)(out + 6) = v6;
+  *(vuint8mf2_t*)(out + 7) = v7;
+  *(vuint8mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
new file mode 100644
index 00000000000..2a597986e2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint16mf4_t v3 = *(vint16mf4_t*)(in + 3);
+  vint16mf4_t v4 = *(vint16mf4_t*)(in + 4);
+  vint16mf4_t v5 = *(vint16mf4_t*)(in + 5);
+  vint16mf4_t v6 = *(vint16mf4_t*)(in + 6);
+  vint16mf4_t v7 = *(vint16mf4_t*)(in + 7);
+  vint16mf4_t v8 = *(vint16mf4_t*)(in + 8);
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint16mf4_t*)(out + 3) = v3;
+  *(vint16mf4_t*)(out + 4) = v4;
+  *(vint16mf4_t*)(out + 5) = v5;
+  *(vint16mf4_t*)(out + 6) = v6;
+  *(vint16mf4_t*)(out + 7) = v7;
+  *(vint16mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint16mf2_t v2 = *(vint16mf2_t*)(in + 2);
+  vint16mf2_t v3 = *(vint16mf2_t*)(in + 3);
+  vint16mf2_t v4 = *(vint16mf2_t*)(in + 4);
+  vint16mf2_t v5 = *(vint16mf2_t*)(in + 5);
+  vint16mf2_t v6 = *(vint16mf2_t*)(in + 6);
+  vint16mf2_t v7 = *(vint16mf2_t*)(in + 7);
+  vint16mf2_t v8 = *(vint16mf2_t*)(in + 8);
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint16mf2_t*)(out + 2) = v2;
+  *(vint16mf2_t*)(out + 3) = v3;
+  *(vint16mf2_t*)(out + 4) = v4;
+  *(vint16mf2_t*)(out + 5) = v5;
+  *(vint16mf2_t*)(out + 6) = v6;
+  *(vint16mf2_t*)(out + 7) = v7;
+  *(vint16mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
new file mode 100644
index 00000000000..982ec8c2567
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vuint16mf4_t v1 = *(vuint16mf4_t*)(in + 1);
+  vuint16mf4_t v2 = *(vuint16mf4_t*)(in + 2);
+  vuint16mf4_t v3 = *(vuint16mf4_t*)(in + 3);
+  vuint16mf4_t v4 = *(vuint16mf4_t*)(in + 4);
+  vuint16mf4_t v5 = *(vuint16mf4_t*)(in + 5);
+  vuint16mf4_t v6 = *(vuint16mf4_t*)(in + 6);
+  vuint16mf4_t v7 = *(vuint16mf4_t*)(in + 7);
+  vuint16mf4_t v8 = *(vuint16mf4_t*)(in + 8);
+  *(vuint16mf4_t*)(out + 1) = v1;
+  *(vuint16mf4_t*)(out + 2) = v2;
+  *(vuint16mf4_t*)(out + 3) = v3;
+  *(vuint16mf4_t*)(out + 4) = v4;
+  *(vuint16mf4_t*)(out + 5) = v5;
+  *(vuint16mf4_t*)(out + 6) = v6;
+  *(vuint16mf4_t*)(out + 7) = v7;
+  *(vuint16mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vuint16mf2_t v1 = *(vuint16mf2_t*)(in + 1);
+  vuint16mf2_t v2 = *(vuint16mf2_t*)(in + 2);
+  vuint16mf2_t v3 = *(vuint16mf2_t*)(in + 3);
+  vuint16mf2_t v4 = *(vuint16mf2_t*)(in + 4);
+  vuint16mf2_t v5 = *(vuint16mf2_t*)(in + 5);
+  vuint16mf2_t v6 = *(vuint16mf2_t*)(in + 6);
+  vuint16mf2_t v7 = *(vuint16mf2_t*)(in + 7);
+  vuint16mf2_t v8 = *(vuint16mf2_t*)(in + 8);
+  *(vuint16mf2_t*)(out + 1) = v1;
+  *(vuint16mf2_t*)(out + 2) = v2;
+  *(vuint16mf2_t*)(out + 3) = v3;
+  *(vuint16mf2_t*)(out + 4) = v4;
+  *(vuint16mf2_t*)(out + 5) = v5;
+  *(vuint16mf2_t*)(out + 6) = v6;
+  *(vuint16mf2_t*)(out + 7) = v7;
+  *(vuint16mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
new file mode 100644
index 00000000000..f75449e7345
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint32mf2_t v2 = *(vint32mf2_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vint32mf2_t v4 = *(vint32mf2_t*)(in + 4);
+  vint32mf2_t v5 = *(vint32mf2_t*)(in + 5);
+  vint32mf2_t v6 = *(vint32mf2_t*)(in + 6);
+  vint32mf2_t v7 = *(vint32mf2_t*)(in + 7);
+  vint32mf2_t v8 = *(vint32mf2_t*)(in + 8);
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vint32mf2_t*)(out + 4) = v4;
+  *(vint32mf2_t*)(out + 5) = v5;
+  *(vint32mf2_t*)(out + 6) = v6;
+  *(vint32mf2_t*)(out + 7) = v7;
+  *(vint32mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
new file mode 100644
index 00000000000..08017e24ef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vuint32mf2_t v1 = *(vuint32mf2_t*)(in + 1);
+  vuint32mf2_t v2 = *(vuint32mf2_t*)(in + 2);
+  vuint32mf2_t v3 = *(vuint32mf2_t*)(in + 3);
+  vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 4);
+  vuint32mf2_t v5 = *(vuint32mf2_t*)(in + 5);
+  vuint32mf2_t v6 = *(vuint32mf2_t*)(in + 6);
+  vuint32mf2_t v7 = *(vuint32mf2_t*)(in + 7);
+  vuint32mf2_t v8 = *(vuint32mf2_t*)(in + 8);
+  *(vuint32mf2_t*)(out + 1) = v1;
+  *(vuint32mf2_t*)(out + 2) = v2;
+  *(vuint32mf2_t*)(out + 3) = v3;
+  *(vuint32mf2_t*)(out + 4) = v4;
+  *(vuint32mf2_t*)(out + 5) = v5;
+  *(vuint32mf2_t*)(out + 6) = v6;
+  *(vuint32mf2_t*)(out + 7) = v7;
+  *(vuint32mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
new file mode 100644
index 00000000000..f03cc5b1b2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vfloat32mf2_t v2 = *(vfloat32mf2_t*)(in + 2);
+  vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  vfloat32mf2_t v5 = *(vfloat32mf2_t*)(in + 5);
+  vfloat32mf2_t v6 = *(vfloat32mf2_t*)(in + 6);
+  vfloat32mf2_t v7 = *(vfloat32mf2_t*)(in + 7);
+  vfloat32mf2_t v8 = *(vfloat32mf2_t*)(in + 8);
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vfloat32mf2_t*)(out + 2) = v2;
+  *(vfloat32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  *(vfloat32mf2_t*)(out + 5) = v5;
+  *(vfloat32mf2_t*)(out + 6) = v6;
+  *(vfloat32mf2_t*)(out + 7) = v7;
+  *(vfloat32mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
new file mode 100644
index 00000000000..e4a734ce616
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
@@ -0,0 +1,147 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint32mf2_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint64m1_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint16mf2_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint16mf2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint32m1_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint32m1_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint64m2_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint64m2_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint16m1_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint16m1_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint32m2_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint32m2_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint64m4_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint64m4_t*)(out + 2) = v2;
+}
+
+void f10 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vint16m2_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vint16m2_t*)(out + 2) = v2;
+}
+
+void f11 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vint32m4_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vint32m4_t*)(out + 2) = v2;
+}
+
+void f12 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vint64m8_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vint64m8_t*)(out + 2) = v2;
+}
+
+void f13 (void * restrict in, void * restrict out)
+{
+  vint8m2_t v1 = *(vint8m2_t*)(in + 1);
+  vint16m4_t v2;
+  *(vint8m2_t*)(out + 1) = v1;
+  *(vint16m4_t*)(out + 2) = v2;
+}
+
+void f14 (void * restrict in, void * restrict out)
+{
+  vint8m2_t v1 = *(vint8m2_t*)(in + 1);
+  vint32m8_t v2;
+  *(vint8m2_t*)(out + 1) = v1;
+  *(vint32m8_t*)(out + 2) = v2;
+}
+
+void f15 (void * restrict in, void * restrict out)
+{
+  vint8m4_t v1 = *(vint8m4_t*)(in + 1);
+  vint16m8_t v2;
+  *(vint8m4_t*)(out + 1) = v1;
+  *(vint16m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
new file mode 100644
index 00000000000..6f0da3a1581
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
@@ -0,0 +1,86 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo1 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void foo4 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void foo5 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void foo6 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void foo7 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
new file mode 100644
index 00000000000..b2dcda61d3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo1 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
new file mode 100644
index 00000000000..28215d7b033
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo1 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
new file mode 100644
index 00000000000..6c485369ca5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
new file mode 100644
index 00000000000..d87c4fb075e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
new file mode 100644
index 00000000000..d8b00b5fce8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
new file mode 100644
index 00000000000..602062c54ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
new file mode 100644
index 00000000000..53659787802
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
