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Thu, 01 Sep 2022 03:24:05 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2813O2hQ32702794 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 Sep 2022 03:24:02 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4305F4203F; Thu, 1 Sep 2022 03:24:02 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5F35942045; Thu, 1 Sep 2022 03:24:01 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 1 Sep 2022 03:24:01 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] Using pli(paddi) and rotate to build 64bit constants Date: Thu, 1 Sep 2022 11:24:00 +0800 Message-Id: <20220901032400.23692-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: TG_QEFwUV8BMra6PPr1ILEbrG3mhr2QQ X-Proofpoint-ORIG-GUID: kbRTokjymdBt0zqitpqet8FYUuF_qn1U X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-09-01_01,2022-08-31_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209010011 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiufu Guo via Gcc-patches From: Jiufu Guo Reply-To: Jiufu Guo Cc: meissner@linux.ibm.com, dje.gcc@gmail.com, segher@kernel.crashing.org, linkw@gcc.gnu.org Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, As mentioned in PR106550, since pli could support 34bits immediate, we could use less instructions(3insn would be ok) to build 64bits constant with pli. For example, for constant 0x020805006106003, we could generate it with: asm code1: pli 9,101736451 (0x6106003) sldi 9,9,32 paddi 9,9, 2130000 (0x0208050) or asm code2: pli 10, 2130000 pli 9, 101736451 rldimi 9, 10, 32, 0 Testing with simple cases as below, run them a lot of times: f1.c long __attribute__ ((noinline)) foo (long *arg,long *,long*) { *arg = 0x2351847027482577; } 5insns: base pli+sldi+paddi: similar -0.08% pli+pli+rldimi: faster +0.66% f2.c long __attribute__ ((noinline)) foo (long *arg, long *arg2, long *arg3) { *arg = 0x2351847027482577; *arg2 = 0x3257845024384680; *arg3 = 0x1245abcef9240dec; } 5nisns: base pli+sldi+paddi: faster +1.35% pli+pli+rldimi: faster +5.49% f2.c would be more meaningful. Because 'sched passes' are effective for f2.c, but 'scheds' do less thing for f1.c. Compare with previous patch: https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599525.html This one updates code slightly and extracts changes on rs6000.md to a seperate patch. This patch pass boostrap and regtest on ppc64le(includes p10). Is it ok for trunk? BR, Jeff(Jiufu) PR target/106550 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add 'pli' for constant building. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr106550.c: New test. --- gcc/config/rs6000/rs6000.cc | 39 +++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr106550.c | 14 ++++++++ 2 files changed, 53 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106550.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index df491bee2ea..1ccb2ff30a1 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10181,6 +10181,45 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) gen_rtx_IOR (DImode, copy_rtx (temp), GEN_INT (ud1))); } + else if (TARGET_PREFIXED) + { + /* pli 9,high32 + pli 10,low32 + rldimi 9,10,32,0. */ + if (can_create_pseudo_p ()) + { + temp = gen_reg_rtx (DImode); + rtx temp1 = gen_reg_rtx (DImode); + emit_move_insn (copy_rtx (temp), GEN_INT ((ud4 << 16) | ud3)); + emit_move_insn (copy_rtx (temp1), GEN_INT ((ud2 << 16) | ud1)); + + emit_insn (gen_rotldi3_insert_3 (dest, temp, GEN_INT (32), temp1, + GEN_INT (0xffffffff))); + } + + /* pli 9,high32 + sldi 9,32 + paddi 9,9,low32. */ + else + { + emit_move_insn (copy_rtx (dest), GEN_INT ((ud4 << 16) | ud3)); + + emit_move_insn (copy_rtx (dest), + gen_rtx_ASHIFT (DImode, copy_rtx (dest), + GEN_INT (32))); + + bool can_use_paddi = REGNO (dest) != FIRST_GPR_REGNO; + + /* Use paddi for the low32 bits. */ + if (ud2 != 0 && ud1 != 0 && can_use_paddi) + emit_move_insn (dest, gen_rtx_PLUS (DImode, copy_rtx (dest), + GEN_INT ((ud2 << 16) | ud1))); + /* Use oris, ori for low32 bits. */ + if (ud2 != 0 && (ud1 == 0 || !can_use_paddi)) + emit_move_insn (ud1 != 0 ? copy_rtx (dest) : dest, + gen_rtx_IOR (DImode, copy_rtx (dest), + GEN_INT (ud2 << 16))); + if (ud1 != 0 && (ud2 == 0 || !can_use_paddi)) + emit_move_insn (dest, gen_rtx_IOR (DImode, copy_rtx (dest), + GEN_INT (ud1))); + } + } else { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550.c b/gcc/testsuite/gcc.target/powerpc/pr106550.c new file mode 100644 index 00000000000..c6f4116bb9a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106550.c @@ -0,0 +1,14 @@ +/* PR target/106550 */ +/* { dg-options "-O2 -std=c99 -mdejagnu-cpu=power10" } */ + +void +foo (unsigned long long *a) +{ + *a++ = 0x020805006106003; + *a++ = 0x2351847027482577; +} + +/* 3 insns for each constant: pli+sldi+paddi or pli+pli+rldimi. + And 3 additional insns: std+std+blr: 9 insns totally. */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9 } } */ +