| Message ID | 20220830015024.17543-1-juzhe.zhong@rivai.ai |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN | expand |
Thanks, pushed with a few minor style fixes. On Tue, Aug 30, 2022 at 9:51 AM <juzhe.zhong@rivai.ai> wrote: > > From: zhongjuzhe <juzhe.zhong@rivai.ai> > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_convert_vector_bits): Change configuration according to TARGET_MIN_VLEN. > * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix annotation. > > --- > gcc/config/riscv/riscv.cc | 11 ++++++----- > gcc/config/riscv/riscv.h | 2 +- > 2 files changed, 7 insertions(+), 6 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 4d439e15392..ef606f33983 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5219,14 +5219,15 @@ riscv_init_machine_status (void) > static poly_uint16 > riscv_convert_vector_bits (void) > { > - /* The runtime invariant is only meaningful when vector is enabled. */ > + /* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */ > if (!TARGET_VECTOR) > return 0; > > - if (TARGET_VECTOR_ELEN_64 || TARGET_VECTOR_ELEN_FP_64) > + if (TARGET_MIN_VLEN > 32) > { > - /* When targetting Zve64* (ELEN = 64) extensions, we should use 64-bit > - chunk size. Runtime invariant: The single indeterminate represent the > + /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. > + Otherwise we can not include sew = 64bits. > + Runtime invariant: The single indeterminate represent the > number of 64-bit chunks in a vector beyond minimum length of 64 bits. > Thus the number of bytes in a vector is 8 + 8 * x1 which is > riscv_vector_chunks * 8 = poly_int (8, 8). */ > @@ -5234,7 +5235,7 @@ riscv_convert_vector_bits (void) > } > else > { > - /* When targetting Zve32* (ELEN = 32) extensions, we should use 32-bit > + /* When targetting minimum VLEN = 32, we should use 32-bit > chunk size. Runtime invariant: The single indeterminate represent the > number of 32-bit chunks in a vector beyond minimum length of 32 bits. > Thus the number of bytes in a vector is 4 + 4 * x1 which is > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 1d8139c2c9b..29582f7c545 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -160,7 +160,7 @@ ASM_MISA_SPEC > > /* The `Q' extension is not yet supported. */ > #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) > -/* Size per vector register. For zve32*, size = poly (4, 4). Otherwise, size = poly (8, 8). */ > +/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ > #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) > > /* The largest type that can be passed in floating-point registers. */ > -- > 2.36.1 >
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4d439e15392..ef606f33983 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5219,14 +5219,15 @@ riscv_init_machine_status (void) static poly_uint16 riscv_convert_vector_bits (void) { - /* The runtime invariant is only meaningful when vector is enabled. */ + /* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */ if (!TARGET_VECTOR) return 0; - if (TARGET_VECTOR_ELEN_64 || TARGET_VECTOR_ELEN_FP_64) + if (TARGET_MIN_VLEN > 32) { - /* When targetting Zve64* (ELEN = 64) extensions, we should use 64-bit - chunk size. Runtime invariant: The single indeterminate represent the + /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. + Otherwise we can not include sew = 64bits. + Runtime invariant: The single indeterminate represent the number of 64-bit chunks in a vector beyond minimum length of 64 bits. Thus the number of bytes in a vector is 8 + 8 * x1 which is riscv_vector_chunks * 8 = poly_int (8, 8). */ @@ -5234,7 +5235,7 @@ riscv_convert_vector_bits (void) } else { - /* When targetting Zve32* (ELEN = 32) extensions, we should use 32-bit + /* When targetting minimum VLEN = 32, we should use 32-bit chunk size. Runtime invariant: The single indeterminate represent the number of 32-bit chunks in a vector beyond minimum length of 32 bits. Thus the number of bytes in a vector is 4 + 4 * x1 which is diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 1d8139c2c9b..29582f7c545 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -160,7 +160,7 @@ ASM_MISA_SPEC /* The `Q' extension is not yet supported. */ #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) -/* Size per vector register. For zve32*, size = poly (4, 4). Otherwise, size = poly (8, 8). */ +/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) /* The largest type that can be passed in floating-point registers. */
From: zhongjuzhe <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Change configuration according to TARGET_MIN_VLEN. * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix annotation. --- gcc/config/riscv/riscv.cc | 11 ++++++----- gcc/config/riscv/riscv.h | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-)