Fix insn does not satisfy its constraints: sse2_lshrv1ti3

21114(define_insn_and_split "ssse3_palignrdi"
21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
21117                    (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv")
21118                    (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
21119                   UNSPEC_PALIGNR))]
21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
which requires AVX512VL & AVX512BW for evex version.

Bootstrapped and regtested on x86_64-pc-linu-gnu{-m32,}.
Ready to push to trunk.

gcc/ChangeLog:

	PR target/105854
	* config/i386/sse.md (ssse3_palignrdi): Change alternative 2
	from Yv to Yw.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr105854.c: New test.
---
 gcc/config/i386/sse.md                   |  6 ++---
 gcc/testsuite/gcc.target/i386/pr105854.c | 32 ++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr105854.c

On Tue, Jun 7, 2022 at 6:56 AM liuhongt via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> 21114(define_insn_and_split "ssse3_palignrdi"
> 21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
> 21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
> 21117                    (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv")
> 21118                    (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
> 21119                   UNSPEC_PALIGNR))]
> 21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
>
> Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
> which requires AVX512VL & AVX512BW for evex version.
>
> Bootstrapped and regtested on x86_64-pc-linu-gnu{-m32,}.
> Ready to push to trunk.
>
> gcc/ChangeLog:
>
>         PR target/105854
>         * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
>         from Yv to Yw.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/i386/pr105854.c: New test.

OK.

Thanks,
Uros.

> ---
>  gcc/config/i386/sse.md                   |  6 ++---
>  gcc/testsuite/gcc.target/i386/pr105854.c | 32 ++++++++++++++++++++++++
>  2 files changed, 35 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr105854.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 62688f8e29d..200308445db 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -21123,9 +21123,9 @@ (define_insn "<ssse3_avx2>_palignr<mode>"
>     (set_attr "mode" "<sseinsnmode>")])
>
>  (define_insn_and_split "ssse3_palignrdi"
> -  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
> -       (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
> -                   (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv")
> +  [(set (match_operand:DI 0 "register_operand" "=y,x,Yw")
> +       (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yw")
> +                   (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yw")
>                     (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
>                    UNSPEC_PALIGNR))]
>    "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
> diff --git a/gcc/testsuite/gcc.target/i386/pr105854.c b/gcc/testsuite/gcc.target/i386/pr105854.c
> new file mode 100644
> index 00000000000..28abef67915
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr105854.c
> @@ -0,0 +1,32 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O -fcaller-saves -mavx512vl -mno-avx512bw" } */
> +
> +typedef int __attribute__((__vector_size__ (8))) T;
> +typedef signed char __attribute__((__vector_size__ (64))) U;
> +typedef int __attribute__((__vector_size__ (16))) V;
> +typedef long long __attribute__((__vector_size__ (8))) W;
> +typedef int __attribute__((__vector_size__ (64))) X;
> +typedef _Decimal128 __attribute__((__vector_size__ (64))) D;
> +
> +D d;
> +T t;
> +U u;
> +V v;
> +W w;
> +
> +void
> +foo (void)
> +{
> +  T t0 = t;
> +  T t1 = (T) __builtin_ia32_palignr (w, (W) { }, 0);
> +  U u1 = __builtin_shufflevector (u, u, 7, 6, 2, 3, 6, 4, 5, 2, 3, 8, 3, 2, 0,
> +                                 4, 0, 6, 2, 2, 5, 3, 1, 0, 7, 5, 3, 3, 7, 6,
> +                                 2, 0, 4, 5, 4, 1, 7, 7, 0, 6, 1, 9, 3, 0, 3,
> +                                 5, 5, 0, 0, 2, 1, 5, 4, 8, 7,
> +                                 2, 1, 1, 6, 4, 9, 9, 1, 5, 0, 2);
> +  V v1 = v;
> +  d += 0.;
> +  U u0 = u + u + u1 + (U) d;
> +  V v0 = ((X)u0)[0] + v + v;
> +  t = (T) (long) (__int128) v0 + t + t + t1;
> +}
> --
> 2.18.1
>