From patchwork Wed Jun 1 02:28:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1637705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LCY8c06cMz9sG6 for ; Wed, 1 Jun 2022 12:32:48 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3ECA2385E010 for ; Wed, 1 Jun 2022 02:32:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id E00933857B99 for ; Wed, 1 Jun 2022 02:30:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E00933857B99 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1654050597tdi1ugoi Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Jun 2022 10:29:56 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: Mzskoac49OiwinxNmSgnf233RsNvdUXdPPP2rDGT4m9WPorAdeyzTaObBBwbc 1ot5Jr2NYIDzIH57eQeq9EB9fYTcPcPFC8vsUIS45qoiKMDD7cA1Ex3P/DTc7fORCPqKHDf oVV0MAzrNORkXtPKhzhfmMVzFyFY6hDtQss5+/f80BS5xaHQeKhiBUlOS1v41vsBjjFUeJc mO8/3ZiYsJe8r1E53VFDNHrolS3G5TZDkiG/Ia1G81AmOmm2KTpw8PCQ7Oa2r2kiBuY14H7 FXkYmgdS/1Hjd4t86VV8qIF+aj08gVsMl2sFuCt3HHPy3LyHHuJlFuAT9HQHvENeWbvbxKj zPB24y6Ko2PaeoylOfR533pO1dGlQ== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 12/34] RISC-V: Add vlsex_2.c Date: Wed, 1 Jun 2022 10:28:55 +0800 Message-Id: <20220601022917.270325-13-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220601022917.270325-1-juzhe.zhong@rivai.ai> References: <20220601022917.270325-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybgforeign:qybgforeign9 X-QQ-Bgrelay: 1 X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhongjuzhe Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: zhongjuzhe gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/intrinsic/vlsex_2.c: New test. --- .../gcc.target/riscv/rvv/intrinsic/vlsex_2.c | 1251 +++++++++++++++++ 1 file changed, 1251 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c new file mode 100644 index 00000000000..a3d8b4fd588 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c @@ -0,0 +1,1251 @@ +/* { dg-do compile } */ +/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include +#include + +/* +** test_vlse8_v_i8mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8mf2_t +test_vlse8_v_i8mf2_m_vl32 (vbool16_t mask, vint8mf2_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m1_t +test_vlse8_v_i8m1_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m1 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m1_t +test_vlse8_v_i8m1_m_vl32 (vbool8_t mask, vint8m1_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m2_t +test_vlse8_v_i8m2_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m2 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m2_t +test_vlse8_v_i8m2_m_vl32 (vbool4_t mask, vint8m2_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m4_t +test_vlse8_v_i8m4_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m4 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m4_t +test_vlse8_v_i8m4_m_vl32 (vbool2_t mask, vint8m4_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m8_t +test_vlse8_v_i8m8_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m8 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m8_t +test_vlse8_v_i8m8_m_vl32 (vbool1_t mask, vint8m8_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16mf4_t +test_vlse16_v_i16mf4_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf4 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16mf4_t +test_vlse16_v_i16mf4_m_vl32 (vbool64_t mask, vint16mf4_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16mf2_t +test_vlse16_v_i16mf2_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf2 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16mf2_t +test_vlse16_v_i16mf2_m_vl32 (vbool32_t mask, vint16mf2_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m1_t +test_vlse16_v_i16m1_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m1 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m1_t +test_vlse16_v_i16m1_m_vl32 (vbool16_t mask, vint16m1_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m2_t +test_vlse16_v_i16m2_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m2 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m2_t +test_vlse16_v_i16m2_m_vl32 (vbool8_t mask, vint16m2_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m4_t +test_vlse16_v_i16m4_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m4 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m4_t +test_vlse16_v_i16m4_m_vl32 (vbool4_t mask, vint16m4_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m8_t +test_vlse16_v_i16m8_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m8 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m8_t +test_vlse16_v_i16m8_m_vl32 (vbool2_t mask, vint16m8_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32mf2_t +test_vlse32_v_i32mf2_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32mf2 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32mf2_t +test_vlse32_v_i32mf2_m_vl32 (vbool64_t mask, vint32mf2_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m1_t +test_vlse32_v_i32m1_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m1 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m1_t +test_vlse32_v_i32m1_m_vl32 (vbool32_t mask, vint32m1_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m2_t +test_vlse32_v_i32m2_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m2 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m2_t +test_vlse32_v_i32m2_m_vl32 (vbool16_t mask, vint32m2_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m4_t +test_vlse32_v_i32m4_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m4 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m4_t +test_vlse32_v_i32m4_m_vl32 (vbool8_t mask, vint32m4_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m8_t +test_vlse32_v_i32m8_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m8 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m8_t +test_vlse32_v_i32m8_m_vl32 (vbool4_t mask, vint32m8_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m1_t +test_vlse64_v_i64m1_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m1 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m1_t +test_vlse64_v_i64m1_m_vl32 (vbool64_t mask, vint64m1_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m2_t +test_vlse64_v_i64m2_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m2 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m2_t +test_vlse64_v_i64m2_m_vl32 (vbool32_t mask, vint64m2_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m4_t +test_vlse64_v_i64m4_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m4 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m4_t +test_vlse64_v_i64m4_m_vl32 (vbool16_t mask, vint64m4_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m8_t +test_vlse64_v_i64m8_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m8 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m8_t +test_vlse64_v_i64m8_m_vl32 (vbool8_t mask, vint64m8_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8mf8_t +test_vlse8_v_u8mf8_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf8 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8mf8_t +test_vlse8_v_u8mf8_m_vl32 (vbool64_t mask, vuint8mf8_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8mf4_t +test_vlse8_v_u8mf4_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf4 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8mf4_t +test_vlse8_v_u8mf4_m_vl32 (vbool32_t mask, vuint8mf4_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8mf2_t +test_vlse8_v_u8mf2_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf2 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8mf2_t +test_vlse8_v_u8mf2_m_vl32 (vbool16_t mask, vuint8mf2_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m1_t +test_vlse8_v_u8m1_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m1 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m1_t +test_vlse8_v_u8m1_m_vl32 (vbool8_t mask, vuint8m1_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m2_t +test_vlse8_v_u8m2_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m2 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m2_t +test_vlse8_v_u8m2_m_vl32 (vbool4_t mask, vuint8m2_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m4_t +test_vlse8_v_u8m4_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m4 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m4_t +test_vlse8_v_u8m4_m_vl32 (vbool2_t mask, vuint8m4_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m8_t +test_vlse8_v_u8m8_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m8 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m8_t +test_vlse8_v_u8m8_m_vl32 (vbool1_t mask, vuint8m8_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16mf4_t +test_vlse16_v_u16mf4_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf4 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16mf4_t +test_vlse16_v_u16mf4_m_vl32 (vbool64_t mask, vuint16mf4_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16mf2_t +test_vlse16_v_u16mf2_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf2 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16mf2_t +test_vlse16_v_u16mf2_m_vl32 (vbool32_t mask, vuint16mf2_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m1_t +test_vlse16_v_u16m1_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m1 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m1_t +test_vlse16_v_u16m1_m_vl32 (vbool16_t mask, vuint16m1_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m2_t +test_vlse16_v_u16m2_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m2 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m2_t +test_vlse16_v_u16m2_m_vl32 (vbool8_t mask, vuint16m2_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m4_t +test_vlse16_v_u16m4_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m4 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m4_t +test_vlse16_v_u16m4_m_vl32 (vbool4_t mask, vuint16m4_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m8_t +test_vlse16_v_u16m8_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m8 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m8_t +test_vlse16_v_u16m8_m_vl32 (vbool2_t mask, vuint16m8_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32mf2_t +test_vlse32_v_u32mf2_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32mf2 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32mf2_t +test_vlse32_v_u32mf2_m_vl32 (vbool64_t mask, vuint32mf2_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m1_t +test_vlse32_v_u32m1_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m1 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m1_t +test_vlse32_v_u32m1_m_vl32 (vbool32_t mask, vuint32m1_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m2_t +test_vlse32_v_u32m2_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m2 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m2_t +test_vlse32_v_u32m2_m_vl32 (vbool16_t mask, vuint32m2_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m4_t +test_vlse32_v_u32m4_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m4 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m4_t +test_vlse32_v_u32m4_m_vl32 (vbool8_t mask, vuint32m4_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m8_t +test_vlse32_v_u32m8_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m8 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m8_t +test_vlse32_v_u32m8_m_vl32 (vbool4_t mask, vuint32m8_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m1_t +test_vlse64_v_u64m1_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m1 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m1_t +test_vlse64_v_u64m1_m_vl32 (vbool64_t mask, vuint64m1_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m2_t +test_vlse64_v_u64m2_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m2 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m2_t +test_vlse64_v_u64m2_m_vl32 (vbool32_t mask, vuint64m2_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m4_t +test_vlse64_v_u64m4_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m4 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m4_t +test_vlse64_v_u64m4_m_vl32 (vbool16_t mask, vuint64m4_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m8_t +test_vlse64_v_u64m8_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m8 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m8_t +test_vlse64_v_u64m8_m_vl32 (vbool8_t mask, vuint64m8_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m8_m (mask, dest, base, bstride, 32); +} +