[v4,12/34] RISC-V: Add vlsex_2.c

Message ID	20220601022917.270325-13-juzhe.zhong@rivai.ai
State	New
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E00933857B99 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 12/34] RISC-V: Add vlsex_2.c Date: Wed, 1 Jun 2022 10:28:55 +0800 Message-Id: <20220601022917.270325-13-juzhe.zhong@rivai.ai> In-Reply-To: <20220601022917.270325-1-juzhe.zhong@rivai.ai> References: <20220601022917.270325-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Feedback-ID: bizesmtp:rivai.ai:qybgforeign:qybgforeign9 Precedence: list Cc: zhongjuzhe <juzhe.zhong@rivai.ai> Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>
Series	RISC-V: Add RVV (RISC-V 'V' Extension) support \| expand [00/34] RISC-V: Add RVV (RISC-V 'V' Extension) support [v4,02/34] RISC-V: Add vlex_2.c [v4,03/34] RISC-V: Add vlex_1.C [v4,04/34] RISC-V: Add mask load store testcases [v4,06/34] RISC-V: Add vlexff_2.c [v4,12/34] RISC-V: Add vlsex_2.c [v4,17/34] RISC-V: Add vsex.c [v4,19/34] RISC-V: Add vssex.c [v4,21/34] RISC-V: Add vlexff_1.C [v4,22/34] RISC-V: Add vloxeix_1.C [v4,23/34] RISC-V: Add vloxeix_2.C [v4,24/34] RISC-V: Add vloxeix_3.C [v4,25/34] RISC-V: Add vloxeix_4.C [v4,26/34] RISC-V: Add vlsex_1.C [v4,27/34] RISC-V: Add vluxeix_1.C [v4,28/34] RISC-V: Add vluxeix_2.C [v4,29/34] RISC-V: Add vluxeix_3.C [v4,30/34] RISC-V: Add vluxeix_4.C [v4,31/34] RISC-V: Add vsex.C [v4,32/34] RISC-V: Add vsoxeix.C [v4,33/34] RISC-V: Add vssex.C [v4,34/34] RISC-V: Add vsuxeix.C

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c new file mode 100644 index 00000000000..a3d8b4fd588 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c @@ -0,0 +1,1251 @@ +/* { dg-do compile } */ +/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include <stddef.h> +#include <riscv_vector.h> + +/* +** test_vlse8_v_i8mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8mf2_t +test_vlse8_v_i8mf2_m_vl32 (vbool16_t mask, vint8mf2_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m1_t +test_vlse8_v_i8m1_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m1 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m1_t +test_vlse8_v_i8m1_m_vl32 (vbool8_t mask, vint8m1_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m2_t +test_vlse8_v_i8m2_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m2 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m2_t +test_vlse8_v_i8m2_m_vl32 (vbool4_t mask, vint8m2_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m4_t +test_vlse8_v_i8m4_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m4 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m4_t +test_vlse8_v_i8m4_m_vl32 (vbool2_t mask, vint8m4_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_i8m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint8m8_t +test_vlse8_v_i8m8_vl32 (int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m8 (base, bstride, 32); +} + +/* +** test_vlse8_v_i8m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint8m8_t +test_vlse8_v_i8m8_m_vl32 (vbool1_t mask, vint8m8_t dest, int8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_i8m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16mf4_t +test_vlse16_v_i16mf4_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf4 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16mf4_t +test_vlse16_v_i16mf4_m_vl32 (vbool64_t mask, vint16mf4_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16mf2_t +test_vlse16_v_i16mf2_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf2 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16mf2_t +test_vlse16_v_i16mf2_m_vl32 (vbool32_t mask, vint16mf2_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m1_t +test_vlse16_v_i16m1_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m1 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m1_t +test_vlse16_v_i16m1_m_vl32 (vbool16_t mask, vint16m1_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m2_t +test_vlse16_v_i16m2_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m2 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m2_t +test_vlse16_v_i16m2_m_vl32 (vbool8_t mask, vint16m2_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m4_t +test_vlse16_v_i16m4_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m4 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m4_t +test_vlse16_v_i16m4_m_vl32 (vbool4_t mask, vint16m4_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_i16m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint16m8_t +test_vlse16_v_i16m8_vl32 (int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m8 (base, bstride, 32); +} + +/* +** test_vlse16_v_i16m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint16m8_t +test_vlse16_v_i16m8_m_vl32 (vbool2_t mask, vint16m8_t dest, int16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_i16m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32mf2_t +test_vlse32_v_i32mf2_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32mf2 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32mf2_t +test_vlse32_v_i32mf2_m_vl32 (vbool64_t mask, vint32mf2_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m1_t +test_vlse32_v_i32m1_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m1 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m1_t +test_vlse32_v_i32m1_m_vl32 (vbool32_t mask, vint32m1_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m2_t +test_vlse32_v_i32m2_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m2 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m2_t +test_vlse32_v_i32m2_m_vl32 (vbool16_t mask, vint32m2_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m4_t +test_vlse32_v_i32m4_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m4 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m4_t +test_vlse32_v_i32m4_m_vl32 (vbool8_t mask, vint32m4_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_i32m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint32m8_t +test_vlse32_v_i32m8_vl32 (int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m8 (base, bstride, 32); +} + +/* +** test_vlse32_v_i32m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint32m8_t +test_vlse32_v_i32m8_m_vl32 (vbool4_t mask, vint32m8_t dest, int32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_i32m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m1_t +test_vlse64_v_i64m1_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m1 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m1_t +test_vlse64_v_i64m1_m_vl32 (vbool64_t mask, vint64m1_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m2_t +test_vlse64_v_i64m2_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m2 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m2_t +test_vlse64_v_i64m2_m_vl32 (vbool32_t mask, vint64m2_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m4_t +test_vlse64_v_i64m4_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m4 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m4_t +test_vlse64_v_i64m4_m_vl32 (vbool16_t mask, vint64m4_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_i64m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vint64m8_t +test_vlse64_v_i64m8_vl32 (int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m8 (base, bstride, 32); +} + +/* +** test_vlse64_v_i64m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vint64m8_t +test_vlse64_v_i64m8_m_vl32 (vbool8_t mask, vint64m8_t dest, int64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_i64m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8mf8_t +test_vlse8_v_u8mf8_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf8 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8mf8_t +test_vlse8_v_u8mf8_m_vl32 (vbool64_t mask, vuint8mf8_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8mf4_t +test_vlse8_v_u8mf4_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf4 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8mf4_t +test_vlse8_v_u8mf4_m_vl32 (vbool32_t mask, vuint8mf4_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8mf2_t +test_vlse8_v_u8mf2_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf2 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8mf2_t +test_vlse8_v_u8mf2_m_vl32 (vbool16_t mask, vuint8mf2_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m1_t +test_vlse8_v_u8m1_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m1 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m1_t +test_vlse8_v_u8m1_m_vl32 (vbool8_t mask, vuint8m1_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m2_t +test_vlse8_v_u8m2_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m2 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m2_t +test_vlse8_v_u8m2_m_vl32 (vbool4_t mask, vuint8m2_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m4_t +test_vlse8_v_u8m4_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m4 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m4_t +test_vlse8_v_u8m4_m_vl32 (vbool2_t mask, vuint8m4_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse8_v_u8m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint8m8_t +test_vlse8_v_u8m8_vl32 (uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m8 (base, bstride, 32); +} + +/* +** test_vlse8_v_u8m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*tu,\s*mu +** ... +** vlse8\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint8m8_t +test_vlse8_v_u8m8_m_vl32 (vbool1_t mask, vuint8m8_t dest, uint8_t *base, ptrdiff_t bstride) +{ + return vlse8_v_u8m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16mf4_t +test_vlse16_v_u16mf4_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf4 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16mf4_t +test_vlse16_v_u16mf4_m_vl32 (vbool64_t mask, vuint16mf4_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16mf2_t +test_vlse16_v_u16mf2_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf2 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16mf2_t +test_vlse16_v_u16mf2_m_vl32 (vbool32_t mask, vuint16mf2_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m1_t +test_vlse16_v_u16m1_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m1 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m1_t +test_vlse16_v_u16m1_m_vl32 (vbool16_t mask, vuint16m1_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m2_t +test_vlse16_v_u16m2_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m2 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m2_t +test_vlse16_v_u16m2_m_vl32 (vbool8_t mask, vuint16m2_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m4_t +test_vlse16_v_u16m4_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m4 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m4_t +test_vlse16_v_u16m4_m_vl32 (vbool4_t mask, vuint16m4_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse16_v_u16m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint16m8_t +test_vlse16_v_u16m8_vl32 (uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m8 (base, bstride, 32); +} + +/* +** test_vlse16_v_u16m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*tu,\s*mu +** ... +** vlse16\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint16m8_t +test_vlse16_v_u16m8_m_vl32 (vbool2_t mask, vuint16m8_t dest, uint16_t *base, ptrdiff_t bstride) +{ + return vlse16_v_u16m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32mf2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32mf2_t +test_vlse32_v_u32mf2_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32mf2 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32mf2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32mf2_t +test_vlse32_v_u32mf2_m_vl32 (vbool64_t mask, vuint32mf2_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32mf2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m1_t +test_vlse32_v_u32m1_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m1 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m1_t +test_vlse32_v_u32m1_m_vl32 (vbool32_t mask, vuint32m1_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m2_t +test_vlse32_v_u32m2_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m2 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m2_t +test_vlse32_v_u32m2_m_vl32 (vbool16_t mask, vuint32m2_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m4_t +test_vlse32_v_u32m4_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m4 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m4_t +test_vlse32_v_u32m4_m_vl32 (vbool8_t mask, vuint32m4_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse32_v_u32m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint32m8_t +test_vlse32_v_u32m8_vl32 (uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m8 (base, bstride, 32); +} + +/* +** test_vlse32_v_u32m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*tu,\s*mu +** ... +** vlse32\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint32m8_t +test_vlse32_v_u32m8_m_vl32 (vbool4_t mask, vuint32m8_t dest, uint32_t *base, ptrdiff_t bstride) +{ + return vlse32_v_u32m8_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m1_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m1_t +test_vlse64_v_u64m1_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m1 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m1_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m1_t +test_vlse64_v_u64m1_m_vl32 (vbool64_t mask, vuint64m1_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m1_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m2_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m2_t +test_vlse64_v_u64m2_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m2 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m2_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m2_t +test_vlse64_v_u64m2_m_vl32 (vbool32_t mask, vuint64m2_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m2_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m4_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m4_t +test_vlse64_v_u64m4_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m4 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m4_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m4_t +test_vlse64_v_u64m4_m_vl32 (vbool16_t mask, vuint64m4_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m4_m (mask, dest, base, bstride, 32); +} + +/* +** test_vlse64_v_u64m8_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*t[au],\s*m[au] +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]) +** ... +** ret +*/ +vuint64m8_t +test_vlse64_v_u64m8_vl32 (uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m8 (base, bstride, 32); +} + +/* +** test_vlse64_v_u64m8_m_vl32: +** ... +** vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*tu,\s*mu +** ... +** vlse64\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*v0\.t +** ... +** ret +*/ +vuint64m8_t +test_vlse64_v_u64m8_m_vl32 (vbool8_t mask, vuint64m8_t dest, uint64_t *base, ptrdiff_t bstride) +{ + return vlse64_v_u64m8_m (mask, dest, base, bstride, 32); +} +

[v4,12/34] RISC-V: Add vlsex_2.c

Commit Message

Patch