diff mbox series

[05/21] Add RVV configuration intrinsic

Message ID 20220531085012.269719-6-juzhe.zhong@rivai.ai
State New
Headers show
Series *** Add RVV (RISC-V 'V' Extension) support *** | expand

Commit Message

钟居哲 May 31, 2022, 8:49 a.m. UTC 
From: zhongjuzhe <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-protos.h (riscv_register_pragmas): New function.
        (riscv_classify_vlmul_field): New enum.
        (rvv_classify_vlmul_field): New enum.
        (rvv_parse_vsew_field): New enum.
        (rvv_parse_vlmul_field): New enum.
        (rvv_parse_vta_field): New enum.
        (rvv_parse_vma_field): New enum.
        * config/riscv/riscv-vector-builtins-functions.cc (get_vtype_for_mode): New function.
        (mode2data_type_str): New function.
        (config::call_properties): New function.
        (config::assemble_name): New function.
        (config::get_return_type): New function.
        (vsetvl::get_argument_types): New function.
        (vsetvl::expand): New function.
        (vsetvlmax::expand): New function.
        * config/riscv/riscv-vector-builtins-functions.def:
        (vsetvl): New macro define.
        (vsetvlmax): New macro define.
        * config/riscv/riscv-vector-builtins-functions.h (class config): New class.
        (class vsetvl): New class.
        (class vsetvlmax): New class.
        * config/riscv/riscv-vector-builtins-iterators.def (VI): New iterator.
        * config/riscv/riscv-vector.cc (rvv_parse_vsew_field): New function.
        (rvv_parse_vlmul_field): New function.
        (rvv_parse_vta_field): New function.
        (rvv_parse_vma_field): New function.
        * config/riscv/riscv-vector.h (rvv_parse_vsew_field): New function.
        (rvv_parse_vlmul_field): New function.
        (rvv_parse_vta_field): New function.
        (rvv_parse_vma_field): New function.
        * config/riscv/riscv.md: Add X0_REGNUM constant.
        * config/riscv/vector-iterators.md (unspec): New unspec.
        * config/riscv/vector.md: New file.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/intrinsic/rvv-intrinsic.exp: New test.
        * gcc.target/riscv/rvv/intrinsic/vsetvl.c: New test.
        
---
 gcc/config/riscv/riscv-protos.h               |   8 +-
 .../riscv/riscv-vector-builtins-functions.cc  | 232 ++++++
 .../riscv/riscv-vector-builtins-functions.def |   6 +
 .../riscv/riscv-vector-builtins-functions.h   |  36 +
 .../riscv/riscv-vector-builtins-iterators.def |  23 +
 gcc/config/riscv/riscv-vector.cc              |  28 +
 gcc/config/riscv/riscv-vector.h               |   4 +
 gcc/config/riscv/riscv.md                     |   6 +-
 gcc/config/riscv/vector-iterators.md          |  14 +-
 gcc/config/riscv/vector.md                    | 140 ++++
 .../riscv/rvv/intrinsic/rvv-intrinsic.exp     |  47 ++
 .../gcc.target/riscv/rvv/intrinsic/vsetvl.c   | 733 ++++++++++++++++++
 12 files changed, 1273 insertions(+), 4 deletions(-)
 create mode 100644 gcc/config/riscv/vector.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/rvv-intrinsic.exp
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsetvl.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4a4ac645f55..cae2974b54f 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -77,6 +77,7 @@  extern bool riscv_gpr_save_operation_p (rtx);
 
 /* Routines implemented in riscv-c.cc.  */
 void riscv_cpu_cpp_builtins (cpp_reader *);
+void riscv_register_pragmas (void);
 
 /* Routines implemented in riscv-d.cc  */
 extern void riscv_d_target_versions (void);
@@ -114,9 +115,12 @@  extern const riscv_cpu_info *riscv_find_cpu (const char *);
 extern bool rvv_mode_p (machine_mode);
 extern bool rvv_legitimate_poly_int_p (rtx);
 extern unsigned int rvv_offset_temporaries (bool, poly_int64);
-extern enum vlmul_field_enum riscv_classify_vlmul_field (machine_mode);
+extern enum vlmul_field_enum rvv_classify_vlmul_field (machine_mode);
+extern unsigned int rvv_parse_vsew_field (unsigned int);
+extern unsigned int rvv_parse_vlmul_field (unsigned int);
+extern bool rvv_parse_vta_field (unsigned int);
+extern bool rvv_parse_vma_field (unsigned int);
 extern int rvv_regsize (machine_mode);
-extern void riscv_register_pragmas (void);
 
 /* We classify builtin types into two classes:
    1. General builtin class which is using the
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.cc b/gcc/config/riscv/riscv-vector-builtins-functions.cc
index 19bcb66a83f..0acda8f671e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.cc
@@ -49,6 +49,164 @@  static const unsigned int CP_WRITE_CSR = 1U << 6;
    when the required extension is disabled.  */
 static bool reported_missing_extension_p;
 
+/* Generate vtype bitmap for a specific machine mode. */
+static unsigned int
+get_vtype_for_mode (machine_mode mode)
+{
+  switch (mode)
+    {
+    case VNx2QImode:
+    case VNx2BImode:
+      return 0x45;
+
+    case VNx4QImode:
+    case VNx4BImode:
+      return 0x46;
+
+    case VNx8QImode:
+    case VNx8BImode:
+      return 0x47;
+
+    case VNx16QImode:
+    case VNx16BImode:
+      return 0x40;
+
+    case VNx32QImode:
+    case VNx32BImode:
+      return 0x41;
+
+    case VNx64QImode:
+    case VNx64BImode:
+      return 0x42;
+
+    case VNx128QImode:
+    case VNx128BImode:
+      return 0x43;
+
+    case VNx2HImode:
+      return 0x4e;
+
+    case VNx4HImode:
+      return 0x4f;
+
+    case VNx8HImode:
+      return 0x48;
+
+    case VNx16HImode:
+      return 0x49;
+
+    case VNx32HImode:
+      return 0x4a;
+
+    case VNx64HImode:
+      return 0x4b;
+
+    case VNx2SImode:
+    case VNx2SFmode:
+      return 0x57;
+
+    case VNx4SImode:
+    case VNx4SFmode:
+      return 0x50;
+
+    case VNx8SImode:
+    case VNx8SFmode:
+      return 0x51;
+
+    case VNx16SImode:
+    case VNx16SFmode:
+      return 0x52;
+
+    case VNx32SImode:
+    case VNx32SFmode:
+      return 0x53;
+
+    case VNx2DImode:
+    case VNx2DFmode:
+      return 0x58;
+
+    case VNx4DImode:
+    case VNx4DFmode:
+      return 0x59;
+
+    case VNx8DImode:
+    case VNx8DFmode:
+      return 0x5a;
+
+    case VNx16DImode:
+      return 0x5b;
+
+    default:
+      break;
+    }
+
+  gcc_unreachable ();
+}
+
+static const char *
+mode2data_type_str (machine_mode mode, bool u, bool ie)
+{
+  switch (mode)
+    {
+  #define MODE2DATA_TYPE_STR(MODE, NBITS, LMUL) \
+    case VNx##MODE##mode: \
+      return ie ? "_e"#NBITS""#LMUL"" : u ? "_u"#NBITS""#LMUL"" : "_i"#NBITS""#LMUL"";
+    MODE2DATA_TYPE_STR (2QI, 8, mf8)
+    MODE2DATA_TYPE_STR (4QI, 8, mf4)
+    MODE2DATA_TYPE_STR (8QI, 8, mf2)
+    MODE2DATA_TYPE_STR (16QI, 8, m1)
+    MODE2DATA_TYPE_STR (32QI, 8, m2)
+    MODE2DATA_TYPE_STR (64QI, 8, m4)
+    MODE2DATA_TYPE_STR (128QI, 8, m8)
+    MODE2DATA_TYPE_STR (2HI, 16, mf4)
+    MODE2DATA_TYPE_STR (4HI, 16, mf2)
+    MODE2DATA_TYPE_STR (8HI, 16, m1)
+    MODE2DATA_TYPE_STR (16HI, 16, m2)
+    MODE2DATA_TYPE_STR (32HI, 16, m4)
+    MODE2DATA_TYPE_STR (64HI, 16, m8)
+    MODE2DATA_TYPE_STR (2SI, 32, mf2)
+    MODE2DATA_TYPE_STR (4SI, 32, m1)
+    MODE2DATA_TYPE_STR (8SI, 32, m2)
+    MODE2DATA_TYPE_STR (16SI, 32, m4)
+    MODE2DATA_TYPE_STR (32SI, 32, m8)
+    MODE2DATA_TYPE_STR (2DI, 64, m1)
+    MODE2DATA_TYPE_STR (4DI, 64, m2)
+    MODE2DATA_TYPE_STR (8DI, 64, m4)
+    MODE2DATA_TYPE_STR (16DI, 64, m8)
+  #undef MODE2DATA_TYPE_STR
+  #define MODE2DATA_TYPE_STR(MODE, NBITS, LMUL) \
+    case VNx##MODE##mode: \
+      return "_f"#NBITS""#LMUL"";
+    MODE2DATA_TYPE_STR (2SF, 32, mf2)
+    MODE2DATA_TYPE_STR (4SF, 32, m1)
+    MODE2DATA_TYPE_STR (8SF, 32, m2)
+    MODE2DATA_TYPE_STR (16SF, 32, m4)
+    MODE2DATA_TYPE_STR (32SF, 32, m8)
+    MODE2DATA_TYPE_STR (2DF, 64, m1)
+    MODE2DATA_TYPE_STR (4DF, 64, m2)
+    MODE2DATA_TYPE_STR (8DF, 64, m4)
+    MODE2DATA_TYPE_STR (16DF, 64, m8)
+  #undef MODE2DATA_TYPE_STR
+  case VNx2BImode: return "_b64";
+  case VNx4BImode: return "_b32";
+  case VNx8BImode: return "_b16";
+  case VNx16BImode: return "_b8"; 
+  case VNx32BImode: return "_b4"; 
+  case VNx64BImode: return "_b2"; 
+  case VNx128BImode: return "_b1";
+  case QImode: return u ? "_u8" : "_i8";
+  case HImode: return u ? "_u16" : "_i16";
+  case SImode: return u ? "_u32" : "_i32";
+  case DImode: return u ? "_u64" : "_i64";
+  case SFmode: return "_f32";
+  case DFmode: return "_f64";
+    default:
+      break;
+    }
+
+  gcc_unreachable ();
+}
+
 static tree
 mode2mask_t (machine_mode mode)
 {
@@ -990,6 +1148,80 @@  function_builder::register_function ()
     }
 }
 
+/* A function implementation for config builder */
+unsigned int
+config::call_properties () const
+{
+  return CP_READ_CSR | CP_WRITE_CSR;
+}
+
+char *
+config::assemble_name (function_instance &instance)
+{
+  machine_mode mode = instance.get_arg_pattern ().arg_list[0];
+  const char *name = instance.get_base_name ();
+  const char *dt = mode2data_type_str (mode, false, true);
+  snprintf (instance.function_name, NAME_MAXLEN, "%s%s", name, dt);
+  return nullptr;
+}
+
+tree
+config::get_return_type (const function_instance &) const
+{
+  return size_type_node;
+}
+
+/* A function implementation for vsetvl builder */
+void
+vsetvl::get_argument_types (const function_instance &,
+                            vec<tree> &argument_types) const
+{
+  argument_types.quick_push (size_type_node);
+}
+
+rtx
+vsetvl::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  struct expand_operand ops[MAX_RECOG_OPERANDS];
+  tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+
+  /* Map any target to operand 0.  */
+  int opno = 0;
+  create_output_operand (&ops[opno++], target, Pmode);
+  unsigned int vtype =
+      get_vtype_for_mode (instance.get_arg_pattern ().arg_list[0]);
+  enum insn_code icode = code_for_vsetvl (Pmode);
+  add_input_operand (&ops[opno++], exp, 0);
+  /* create vtype input operand.  */
+  create_input_operand (&ops[opno++], GEN_INT (vtype), Pmode);
+  /* Map the arguments to the other operands.  */
+  gcc_assert (opno == insn_data[icode].n_generator_args);
+  return generate_builtin_insn (icode, opno, ops,
+                                !function_returns_void_p (fndecl));
+}
+
+/* A function implementation for vsetvlmax builder */
+rtx
+vsetvlmax::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  struct expand_operand ops[MAX_RECOG_OPERANDS];
+  tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+
+  /* Map any target to operand 0.  */
+  int opno = 0;
+  create_output_operand (&ops[opno++], target, Pmode);
+  unsigned int vtype =
+      get_vtype_for_mode (instance.get_arg_pattern ().arg_list[0]);
+  enum insn_code icode = code_for_vsetvl (Pmode);
+  create_input_operand (&ops[opno++], gen_rtx_REG (Pmode, X0_REGNUM), Pmode);
+  /* create vtype input operand.  */
+  create_input_operand (&ops[opno++], GEN_INT (vtype), Pmode);
+  /* Map the arguments to the other operands.  */
+  gcc_assert (opno == insn_data[icode].n_generator_args);
+  return generate_builtin_insn (icode, opno, ops,
+                                !function_returns_void_p (fndecl));
+}
+
 } // end namespace riscv_vector
 
 using namespace riscv_vector;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index f6161012813..666e8503d81 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -29,6 +29,12 @@  along with GCC; see the file COPYING3. If not see
 #define VATTR(A, B)
 #endif
 
+/* base_name, class_name, arg_pattern, intrinsic_type, pred_type, operation_type */
+#define REQUIRED_EXTENSIONS (RISCV_TARGET_VECTOR)
+/* 6. Configuration-Setting Instructions. */
+DEF_RVV_FUNCTION(vsetvl, vsetvl, (1, VITER(VI, signed)), PAT_none, PRED_none, OP_none)
+DEF_RVV_FUNCTION(vsetvlmax, vsetvlmax, (1, VITER(VI, signed)), PAT_none, PRED_none, OP_none)
+#undef REQUIRED_EXTENSIONS
 #undef DEF_RVV_FUNCTION
 #undef VITER
 #undef VATTR
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.h b/gcc/config/riscv/riscv-vector-builtins-functions.h
index 1b769743857..9846ded1155 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.h
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.h
@@ -486,6 +486,42 @@  struct registered_function_hasher : nofree_ptr_hash<registered_function>
   static bool equal (value_type, const compare_type &);
 };
 
+/* A function_base for config functions.  */
+class config : public function_builder
+{
+public:
+  // use the same construction function as the function_builder
+  using function_builder::function_builder;
+
+  virtual unsigned int call_properties () const override;
+  
+  virtual char * assemble_name (function_instance &) override;
+  
+  virtual tree get_return_type (const function_instance &) const override;
+};
+
+/* A function_base for vsetvl functions.  */
+class vsetvl : public config
+{
+public:
+  // use the same construction function as the config
+  using config::config;
+  
+  virtual void get_argument_types (const function_instance &, vec<tree> &) const override;
+  
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
+/* A function_base for config functions.  */
+class vsetvlmax : public config
+{
+public:
+  // use the same construction function as the config
+  using config::config;
+  
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
 } // namespace riscv_vector
 
 #endif // end GCC_RISCV_VECTOR_BUILTINS_FUNCTIONS_H
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-vector-builtins-iterators.def b/gcc/config/riscv/riscv-vector-builtins-iterators.def
index ac0c37e12d4..cc968f5534f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-iterators.def
+++ b/gcc/config/riscv/riscv-vector-builtins-iterators.def
@@ -7,6 +7,29 @@ 
 #define DEF_RISCV_ARG_MODE_ATTR(A, B, C, D, E)
 #endif
 
+DEF_RISCV_ARG_MODE_ATTR_VARIABLE(VI, 22)
+DEF_RISCV_ARG_MODE_ATTR(VI, 0, VNx2QI, VNx2QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 1, VNx4QI, VNx4QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 2, VNx8QI, VNx8QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 3, VNx16QI, VNx16QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 4, VNx32QI, VNx32QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 5, VNx64QI, VNx64QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 6, VNx128QI, VNx128QI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 7, VNx2HI, VNx2HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 8, VNx4HI, VNx4HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 9, VNx8HI, VNx8HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 10, VNx16HI, VNx16HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 11, VNx32HI, VNx32HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 12, VNx64HI, VNx64HI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 13, VNx2SI, VNx2SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 14, VNx4SI, VNx4SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 15, VNx8SI, VNx8SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 16, VNx16SI, VNx16SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 17, VNx32SI, VNx32SI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 18, VNx2DI, VNx2DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 19, VNx4DI, VNx4DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 20, VNx8DI, VNx8DI, TARGET_ANY)
+DEF_RISCV_ARG_MODE_ATTR(VI, 21, VNx16DI, VNx16DI, TARGET_ANY)
 
 #undef DEF_RISCV_ARG_MODE_ATTR_VARIABLE
 #undef DEF_RISCV_ARG_MODE_ATTR
diff --git a/gcc/config/riscv/riscv-vector.cc b/gcc/config/riscv/riscv-vector.cc
index 87dc6739f4f..a9c8b290104 100644
--- a/gcc/config/riscv/riscv-vector.cc
+++ b/gcc/config/riscv/riscv-vector.cc
@@ -205,6 +205,34 @@  rvv_classify_vlmul_field (machine_mode mode)
 	gcc_unreachable ();
 }
 
+/* Return the vsew field for a vtype bitmap. */
+unsigned int
+rvv_parse_vsew_field (unsigned int vtype)
+{
+  return (vtype >> 3) & 0x7;
+}
+
+/* Return the vlmul field for a vtype bitmap. */
+unsigned int
+rvv_parse_vlmul_field (unsigned int vtype)
+{
+  return vtype & 0x7;
+}
+
+/* Return the vta field for a vtype bitmap. */
+bool
+rvv_parse_vta_field (unsigned int vtype)
+{
+  return (vtype & 0x40) != 0;
+}
+
+/* Return the vma field for a vtype bitmap. */
+bool
+rvv_parse_vma_field (unsigned int vtype)
+{
+  return (vtype & 0x80) != 0;
+}
+
 /* Return vlmul register size for a machine mode. */
 
 int
diff --git a/gcc/config/riscv/riscv-vector.h b/gcc/config/riscv/riscv-vector.h
index 62df507e7df..2c242959077 100644
--- a/gcc/config/riscv/riscv-vector.h
+++ b/gcc/config/riscv/riscv-vector.h
@@ -24,6 +24,10 @@  bool riscv_vector_mode_p (machine_mode);
 bool rvv_legitimate_poly_int_p (rtx);
 unsigned int rvv_offset_temporaries (bool, poly_int64);
 vlmul_field_enum rvv_classify_vlmul_field (machine_mode);
+extern unsigned int rvv_parse_vsew_field (unsigned int);
+extern unsigned int rvv_parse_vlmul_field (unsigned int);
+extern bool rvv_parse_vta_field (unsigned int);
+extern bool rvv_parse_vma_field (unsigned int);
 int rvv_regsize (machine_mode);
 opt_machine_mode rvv_get_mask_mode (machine_mode);
 #endif // GCC_RISCV_VECTOR_H
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 8e880ba8599..2b0b76458a7 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -106,6 +106,7 @@ 
    ;; Constant helper for RVV 
    (VL_REGNUM			66)
    (VTYPE_REGNUM		67)
+   (X0_REGNUM			0)
 ])
 
 (include "predicates.md")
@@ -182,10 +183,12 @@ 
 ;; nop		no operation
 ;; ghost	an instruction that produces no real code
 ;; bitmanip	bit manipulation instructions
+;; vsetvl vector configuration setting
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
-   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
+   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
+   vsetvl"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,
@@ -2952,3 +2955,4 @@ 
 (include "pic.md")
 (include "generic.md")
 (include "sifive-7.md")
+(include "vector.md")
\ No newline at end of file
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 450e20c44ce..3e0699de86c 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -16,4 +16,16 @@ 
 ;;
 ;; You should have received a copy of the GNU General Public License
 ;; along with GCC; see the file COPYING3.  If not see
-;; <http://www.gnu.org/licenses/>.
\ No newline at end of file
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+  ;; vsetvli.
+  UNSPEC_VSETVLI
+])
+
+;; All integer vector modes supported for RVV.
+(define_mode_iterator VI [
+  VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI VNx64QI VNx128QI
+  VNx2HI VNx4HI VNx8HI VNx16HI VNx32HI VNx64HI
+  VNx2SI VNx4SI VNx8SI VNx16SI VNx32SI
+  VNx2DI VNx4DI VNx8DI VNx16DI])
\ No newline at end of file
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
new file mode 100644
index 00000000000..31fdec981b9
--- /dev/null
+++ b/gcc/config/riscv/vector.md
@@ -0,0 +1,140 @@ 
+;; Machine description for RISC-V vector operations.
+;; Copyright (C) 2022-2022 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; This file describes the RISC-V instructions from the standard 'V' Vector
+;; extension, version 1.0.
+;;
+;; This file include :
+;;
+;; - RVV intrinsic implmentation (Document:https://github.com/riscv/rvv-intrinsic-doc)
+
+(include "vector-iterators.md")
+;; ===============================================================================
+;; == Intrinsics
+;; ===============================================================================
+
+;; -------------------------------------------------------------------------------
+;; ---- 6. Configuration-Setting Instructions
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - 6.1 vsetvli/vsetivl/vsetvl instructions
+;; -------------------------------------------------------------------------------
+
+;; we dont't define vsetvli as unspec_volatile,
+;; because we want this instruction can be scheduling
+;; in the future.
+;; This means these instructions will be deleted when
+;; there is no instructions using vl or vtype in the following.
+;; rd  | rs1 | AVL value | Effect on vl
+;; -   | !x0 | x[rs1]    | Normal stripmining
+;; !x0 | x0  | ~0        | Set vl to VLMAX
+(define_insn "@vsetvl_<mode>"
+  [(parallel
+    [(set (match_operand:X 0 "register_operand" "=r")
+      (unspec:X
+        [(match_operand:X 1 "csr_operand" "rK")] UNSPEC_VSETVLI))
+     (set (reg:SI VL_REGNUM)
+       (unspec:SI
+        [(match_dup 1)] UNSPEC_VSETVLI))
+     (set (reg:SI VTYPE_REGNUM)
+       (unspec:SI
+        [(match_operand 2 "const_int_operand")] UNSPEC_VSETVLI))])]
+  "TARGET_VECTOR"
+  {
+    char buf[64];
+    gcc_assert (CONST_INT_P (operands[2]));
+    const char *insn = satisfies_constraint_K (operands[1]) ? "vsetivli\t%0,%1"
+        : "vsetvli\t%0,%1";
+    unsigned int vsew = rvv_parse_vsew_field (INTVAL (operands[2]));
+    unsigned int vlmul = rvv_parse_vlmul_field (INTVAL (operands[2]));
+    unsigned int vta = rvv_parse_vta_field (INTVAL (operands[2]));
+    unsigned int vma = rvv_parse_vma_field (INTVAL (operands[2]));
+    const char *sew = vsew == 0 ? "e8"  : vsew == 1 ? "e16"
+          : vsew == 2 ? "e32" : "e64";
+    const char *lmul = vlmul == 0 ? "m1" : vlmul == 1 ? "m2"
+          : vlmul == 2 ? "m4" : vlmul == 3 ? "m8"
+          : vlmul == 5 ? "mf8" : vlmul == 6 ? "mf4" : "mf2";
+    const char *ta = vta == 0 ? "tu" : "ta";
+    const char *ma = vma == 0 ? "mu" : "ma";
+    snprintf (buf, sizeof (buf), "%s,%s,%s,%s,%s", insn, sew, lmul, ta, ma);
+    output_asm_insn (buf, operands);
+    return "";
+  }
+  [(set_attr "type" "vsetvl")
+   (set_attr "mode" "none")])
+
+(define_insn "vsetvl_zero_zero"
+  [(set (reg:SI VTYPE_REGNUM)
+    (unspec:SI
+      [(match_operand 0 "const_int_operand")] UNSPEC_VSETVLI))]
+  "TARGET_VECTOR"
+  {
+    char buf[64];
+    gcc_assert (CONST_INT_P (operands[0]));
+    const char *insn = "vsetvli\tzero,zero";
+    unsigned int vsew = rvv_parse_vsew_field (INTVAL (operands[0]));
+    unsigned int vlmul = rvv_parse_vlmul_field (INTVAL (operands[0]));
+    unsigned int vta = rvv_parse_vta_field (INTVAL (operands[0]));
+    unsigned int vma = rvv_parse_vma_field (INTVAL (operands[0]));
+    const char *sew = vsew == 0 ? "e8"  : vsew == 1 ? "e16"
+          : vsew == 2 ? "e32" : "e64";
+    const char *lmul = vlmul == 0 ? "m1" : vlmul == 1 ? "m2"
+          : vlmul == 2 ? "m4" : vlmul == 3 ? "m8"
+          : vlmul == 5 ? "mf8" : vlmul == 6 ? "mf4" : "mf2";
+    const char *ta = vta == 0 ? "tu" : "ta";
+    const char *ma = vma == 0 ? "mu" : "ma";
+    snprintf (buf, sizeof (buf), "%s,%s,%s,%s,%s", insn, sew, lmul, ta, ma);
+    output_asm_insn (buf, operands);
+    return "";
+  }
+  [(set_attr "type" "vsetvl")
+   (set_attr "mode" "none")])
+
+(define_insn "@vsetvl_zero_<mode>"
+  [(parallel
+    [(set (reg:SI VL_REGNUM)
+       (unspec:SI
+        [(match_operand:X 0 "csr_operand" "rK")] UNSPEC_VSETVLI))
+     (set (reg:SI VTYPE_REGNUM)
+       (unspec:SI
+        [(match_operand 1 "const_int_operand")] UNSPEC_VSETVLI))])]
+  "TARGET_VECTOR"
+  {
+    char buf[64];
+    gcc_assert (CONST_INT_P (operands[1]));
+    const char *insn = satisfies_constraint_K (operands[0]) ? "vsetivli\tzero,%0"
+        : "vsetvli\tzero,%0";
+    unsigned int vsew = rvv_parse_vsew_field (INTVAL (operands[1]));
+    unsigned int vlmul = rvv_parse_vlmul_field (INTVAL (operands[1]));
+    unsigned int vta = rvv_parse_vta_field (INTVAL (operands[1]));
+    unsigned int vma = rvv_parse_vma_field (INTVAL (operands[1]));
+    const char *sew = vsew == 0 ? "e8"  : vsew == 1 ? "e16"
+          : vsew == 2 ? "e32" : "e64";
+    const char *lmul = vlmul == 0 ? "m1" : vlmul == 1 ? "m2"
+          : vlmul == 2 ? "m4" : vlmul == 3 ? "m8"
+          : vlmul == 5 ? "mf8" : vlmul == 6 ? "mf4" : "mf2";
+    const char *ta = vta == 0 ? "tu" : "ta";
+    const char *ma = vma == 0 ? "mu" : "ma";
+    snprintf (buf, sizeof (buf), "%s,%s,%s,%s,%s", insn, sew, lmul, ta, ma);
+    output_asm_insn (buf, operands);
+    return "";
+  }
+  [(set_attr "type" "vsetvl")
+   (set_attr "mode" "none")])
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/rvv-intrinsic.exp b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/rvv-intrinsic.exp
new file mode 100644
index 00000000000..b6c66e88759
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/rvv-intrinsic.exp
@@ -0,0 +1,47 @@ 
+# Copyright (C) 2022-2022 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+set gcc_march "rv64gcv_zfh"
+if [istarget riscv32-*-*] then {
+  set gcc_march "rv32gcv_zfh"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O3"
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsetvl.c b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsetvl.c
new file mode 100644
index 00000000000..264537de402
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsetvl.c
@@ -0,0 +1,733 @@ 
+
+/* { dg-do compile } */
+/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+
+#include <stddef.h>
+#include <riscv_vector.h>
+
+
+size_t test_vsetvl_e8mf8_imm0()
+{
+  size_t vl = vsetvl_e8mf8(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf8_imm31()
+{
+  size_t vl = vsetvl_e8mf8(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf8_imm32()
+{
+  size_t vl = vsetvl_e8mf8(32);
+  return vl;
+}
+size_t test_vsetvl_e8mf8(size_t avl)
+{
+  size_t vl = vsetvl_e8mf8(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8mf8()
+{
+  size_t vl = vsetvlmax_e8mf8();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf4_imm0()
+{
+  size_t vl = vsetvl_e8mf4(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf4_imm31()
+{
+  size_t vl = vsetvl_e8mf4(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf4_imm32()
+{
+  size_t vl = vsetvl_e8mf4(32);
+  return vl;
+}
+size_t test_vsetvl_e8mf4(size_t avl)
+{
+  size_t vl = vsetvl_e8mf4(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8mf4()
+{
+  size_t vl = vsetvlmax_e8mf4();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf2_imm0()
+{
+  size_t vl = vsetvl_e8mf2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf2_imm31()
+{
+  size_t vl = vsetvl_e8mf2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8mf2_imm32()
+{
+  size_t vl = vsetvl_e8mf2(32);
+  return vl;
+}
+size_t test_vsetvl_e8mf2(size_t avl)
+{
+  size_t vl = vsetvl_e8mf2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8mf2()
+{
+  size_t vl = vsetvlmax_e8mf2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m1_imm0()
+{
+  size_t vl = vsetvl_e8m1(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m1_imm31()
+{
+  size_t vl = vsetvl_e8m1(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m1_imm32()
+{
+  size_t vl = vsetvl_e8m1(32);
+  return vl;
+}
+size_t test_vsetvl_e8m1(size_t avl)
+{
+  size_t vl = vsetvl_e8m1(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8m1()
+{
+  size_t vl = vsetvlmax_e8m1();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m2_imm0()
+{
+  size_t vl = vsetvl_e8m2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m2_imm31()
+{
+  size_t vl = vsetvl_e8m2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m2_imm32()
+{
+  size_t vl = vsetvl_e8m2(32);
+  return vl;
+}
+size_t test_vsetvl_e8m2(size_t avl)
+{
+  size_t vl = vsetvl_e8m2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8m2()
+{
+  size_t vl = vsetvlmax_e8m2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m4_imm0()
+{
+  size_t vl = vsetvl_e8m4(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m4_imm31()
+{
+  size_t vl = vsetvl_e8m4(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m4_imm32()
+{
+  size_t vl = vsetvl_e8m4(32);
+  return vl;
+}
+size_t test_vsetvl_e8m4(size_t avl)
+{
+  size_t vl = vsetvl_e8m4(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8m4()
+{
+  size_t vl = vsetvlmax_e8m4();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m8_imm0()
+{
+  size_t vl = vsetvl_e8m8(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m8_imm31()
+{
+  size_t vl = vsetvl_e8m8(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e8m8_imm32()
+{
+  size_t vl = vsetvl_e8m8(32);
+  return vl;
+}
+size_t test_vsetvl_e8m8(size_t avl)
+{
+  size_t vl = vsetvl_e8m8(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e8m8()
+{
+  size_t vl = vsetvlmax_e8m8();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16mf4_imm0()
+{
+  size_t vl = vsetvl_e16mf4(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16mf4_imm31()
+{
+  size_t vl = vsetvl_e16mf4(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16mf4_imm32()
+{
+  size_t vl = vsetvl_e16mf4(32);
+  return vl;
+}
+size_t test_vsetvl_e16mf4(size_t avl)
+{
+  size_t vl = vsetvl_e16mf4(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e16mf4()
+{
+  size_t vl = vsetvlmax_e16mf4();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16mf2_imm0()
+{
+  size_t vl = vsetvl_e16mf2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16mf2_imm31()
+{
+  size_t vl = vsetvl_e16mf2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16mf2_imm32()
+{
+  size_t vl = vsetvl_e16mf2(32);
+  return vl;
+}
+size_t test_vsetvl_e16mf2(size_t avl)
+{
+  size_t vl = vsetvl_e16mf2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e16mf2()
+{
+  size_t vl = vsetvlmax_e16mf2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m1_imm0()
+{
+  size_t vl = vsetvl_e16m1(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m1_imm31()
+{
+  size_t vl = vsetvl_e16m1(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m1_imm32()
+{
+  size_t vl = vsetvl_e16m1(32);
+  return vl;
+}
+size_t test_vsetvl_e16m1(size_t avl)
+{
+  size_t vl = vsetvl_e16m1(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e16m1()
+{
+  size_t vl = vsetvlmax_e16m1();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m2_imm0()
+{
+  size_t vl = vsetvl_e16m2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m2_imm31()
+{
+  size_t vl = vsetvl_e16m2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m2_imm32()
+{
+  size_t vl = vsetvl_e16m2(32);
+  return vl;
+}
+size_t test_vsetvl_e16m2(size_t avl)
+{
+  size_t vl = vsetvl_e16m2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e16m2()
+{
+  size_t vl = vsetvlmax_e16m2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m4_imm0()
+{
+  size_t vl = vsetvl_e16m4(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m4_imm31()
+{
+  size_t vl = vsetvl_e16m4(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m4_imm32()
+{
+  size_t vl = vsetvl_e16m4(32);
+  return vl;
+}
+size_t test_vsetvl_e16m4(size_t avl)
+{
+  size_t vl = vsetvl_e16m4(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e16m4()
+{
+  size_t vl = vsetvlmax_e16m4();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m8_imm0()
+{
+  size_t vl = vsetvl_e16m8(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m8_imm31()
+{
+  size_t vl = vsetvl_e16m8(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e16m8_imm32()
+{
+  size_t vl = vsetvl_e16m8(32);
+  return vl;
+}
+size_t test_vsetvl_e16m8(size_t avl)
+{
+  size_t vl = vsetvl_e16m8(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e16m8()
+{
+  size_t vl = vsetvlmax_e16m8();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32mf2_imm0()
+{
+  size_t vl = vsetvl_e32mf2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32mf2_imm31()
+{
+  size_t vl = vsetvl_e32mf2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32mf2_imm32()
+{
+  size_t vl = vsetvl_e32mf2(32);
+  return vl;
+}
+size_t test_vsetvl_e32mf2(size_t avl)
+{
+  size_t vl = vsetvl_e32mf2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e32mf2()
+{
+  size_t vl = vsetvlmax_e32mf2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m1_imm0()
+{
+  size_t vl = vsetvl_e32m1(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m1_imm31()
+{
+  size_t vl = vsetvl_e32m1(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m1_imm32()
+{
+  size_t vl = vsetvl_e32m1(32);
+  return vl;
+}
+size_t test_vsetvl_e32m1(size_t avl)
+{
+  size_t vl = vsetvl_e32m1(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e32m1()
+{
+  size_t vl = vsetvlmax_e32m1();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m2_imm0()
+{
+  size_t vl = vsetvl_e32m2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m2_imm31()
+{
+  size_t vl = vsetvl_e32m2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m2_imm32()
+{
+  size_t vl = vsetvl_e32m2(32);
+  return vl;
+}
+size_t test_vsetvl_e32m2(size_t avl)
+{
+  size_t vl = vsetvl_e32m2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e32m2()
+{
+  size_t vl = vsetvlmax_e32m2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m4_imm0()
+{
+  size_t vl = vsetvl_e32m4(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m4_imm31()
+{
+  size_t vl = vsetvl_e32m4(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m4_imm32()
+{
+  size_t vl = vsetvl_e32m4(32);
+  return vl;
+}
+size_t test_vsetvl_e32m4(size_t avl)
+{
+  size_t vl = vsetvl_e32m4(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e32m4()
+{
+  size_t vl = vsetvlmax_e32m4();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m8_imm0()
+{
+  size_t vl = vsetvl_e32m8(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m8_imm31()
+{
+  size_t vl = vsetvl_e32m8(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e32m8_imm32()
+{
+  size_t vl = vsetvl_e32m8(32);
+  return vl;
+}
+size_t test_vsetvl_e32m8(size_t avl)
+{
+  size_t vl = vsetvl_e32m8(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e32m8()
+{
+  size_t vl = vsetvlmax_e32m8();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m1_imm0()
+{
+  size_t vl = vsetvl_e64m1(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m1_imm31()
+{
+  size_t vl = vsetvl_e64m1(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m1_imm32()
+{
+  size_t vl = vsetvl_e64m1(32);
+  return vl;
+}
+size_t test_vsetvl_e64m1(size_t avl)
+{
+  size_t vl = vsetvl_e64m1(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e64m1()
+{
+  size_t vl = vsetvlmax_e64m1();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m2_imm0()
+{
+  size_t vl = vsetvl_e64m2(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m2_imm31()
+{
+  size_t vl = vsetvl_e64m2(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m2_imm32()
+{
+  size_t vl = vsetvl_e64m2(32);
+  return vl;
+}
+size_t test_vsetvl_e64m2(size_t avl)
+{
+  size_t vl = vsetvl_e64m2(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e64m2()
+{
+  size_t vl = vsetvlmax_e64m2();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m4_imm0()
+{
+  size_t vl = vsetvl_e64m4(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m4_imm31()
+{
+  size_t vl = vsetvl_e64m4(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m4_imm32()
+{
+  size_t vl = vsetvl_e64m4(32);
+  return vl;
+}
+size_t test_vsetvl_e64m4(size_t avl)
+{
+  size_t vl = vsetvl_e64m4(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e64m4()
+{
+  size_t vl = vsetvlmax_e64m4();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m8_imm0()
+{
+  size_t vl = vsetvl_e64m8(0);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m8_imm31()
+{
+  size_t vl = vsetvl_e64m8(31);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
+
+size_t test_vsetvl_e64m8_imm32()
+{
+  size_t vl = vsetvl_e64m8(32);
+  return vl;
+}
+size_t test_vsetvl_e64m8(size_t avl)
+{
+  size_t vl = vsetvl_e64m8(avl);
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*ta,\s*mu} 2 } } */
+
+size_t test_vsetvlmax_e64m8()
+{
+  size_t vl = vsetvlmax_e64m8();
+  return vl;
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */