From patchwork Wed Feb 2 00:24:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1587497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=AyRbWXBq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JpN046P53z9sFq for ; Wed, 2 Feb 2022 11:26:44 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AFDA13858437 for ; Wed, 2 Feb 2022 00:26:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AFDA13858437 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1643761602; bh=QXVqjnO1a/rGl5+0Xed6ZgypfSiD83bZmdImUSnOZ4E=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=AyRbWXBqQIJjvgs7FGzuNG8wqFJ6PCbxEif+7Nzoru4MCuFB4AierVug3BfehnIQh jHsp6eC2XNl1cJosNUBmjk8aNCj75t8s8dFAHmbMAJyreHQPDbhhcZhOAQFXXdo1Jq K8RveDOopqHBHVsbF/BYPadpk4RD5V2/0g4xuRW0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by sourceware.org (Postfix) with ESMTPS id 972F23857C47 for ; Wed, 2 Feb 2022 00:24:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 972F23857C47 To: Subject: [PATCH 3/5] cris: Remove CRIS v32 ACR artefacts MIME-Version: 1.0 Message-ID: <20220202002401.4305620439@pchp3.se.axis.com> Date: Wed, 2 Feb 2022 01:24:01 +0100 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This is the change to which I alluded to this in r11-220 / d0780379c1b6 as "causes extra register moves in libgcc". It has unfortunate side-effects due to the change in register-class topology. There's a slight improvement in coremark numbers (< 0.07%) though also increase in code size total (< 0.7%) but looking at the individual changes in functions, it's all-over (-7..+7%). Looking specifically at functions that improved in speed, it's also both plus and minus in code sizes. It's unworkable to separate improvements from regressions for this case. I'll follow up with patches to restore the previous code quality, in both size and speed. gcc: * config/cris/constraints.md (define_register_constraint "b"): Now GENERAL_REGS. * config/cris/cris.md (CRIS_ACR_REGNUM): Remove. * config/cris/cris.h: (reg_class, REG_CLASS_NAMES) (REG_CLASS_CONTENTS): Remove ACR_REGS, SPEC_ACR_REGS, GENNONACR_REGS, and SPEC_GENNONACR_REGS. * config/cris/cris.cc (cris_preferred_reload_class): Don't mention ACR_REGS and return GENERAL_REGS instead of GENNONACR_REGS. --- gcc/config/cris/constraints.md | 7 ++++++- gcc/config/cris/cris.cc | 5 ++--- gcc/config/cris/cris.h | 27 +++++---------------------- gcc/config/cris/cris.md | 1 - 4 files changed, 13 insertions(+), 27 deletions(-) diff --git a/gcc/config/cris/constraints.md b/gcc/config/cris/constraints.md index 01ec12c4cf2a..83fab622717d 100644 --- a/gcc/config/cris/constraints.md +++ b/gcc/config/cris/constraints.md @@ -18,7 +18,12 @@ ;; . ;; Register constraints. -(define_register_constraint "b" "GENNONACR_REGS" + +;; Kept for compatibility. It used to exclude the CRIS v32 +;; register "ACR", which was like GENERAL_REGS except it +;; couldn't be used for autoincrement, and intended mainly +;; for use in user asm statements. +(define_register_constraint "b" "GENERAL_REGS" "@internal") (define_register_constraint "h" "MOF_REGS" diff --git a/gcc/config/cris/cris.cc b/gcc/config/cris/cris.cc index a7807b3cc25c..264439c7654a 100644 --- a/gcc/config/cris/cris.cc +++ b/gcc/config/cris/cris.cc @@ -1663,13 +1663,12 @@ cris_reload_address_legitimized (rtx x, static reg_class_t cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) { - if (rclass != ACR_REGS - && rclass != MOF_REGS + if (rclass != MOF_REGS && rclass != MOF_SRP_REGS && rclass != SRP_REGS && rclass != CC0_REGS && rclass != SPECIAL_REGS) - return GENNONACR_REGS; + return GENERAL_REGS; return rclass; } diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 9245d7886929..6edfe13d92cc 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -436,19 +436,15 @@ extern int cris_cpu_version; /* Node: Register Classes */ -/* We need a separate register class to handle register allocation for - ACR, since it can't be used for post-increment. - - It's not obvious, but having subunions of all movable-between +/* It's not obvious, but having subunions of all movable-between register classes does really help register allocation (pre-IRA comment). */ enum reg_class { NO_REGS, - ACR_REGS, MOF_REGS, SRP_REGS, CC0_REGS, + MOF_REGS, SRP_REGS, CC0_REGS, MOF_SRP_REGS, SPECIAL_REGS, - SPEC_ACR_REGS, GENNONACR_REGS, - SPEC_GENNONACR_REGS, GENERAL_REGS, + GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -457,9 +453,8 @@ enum reg_class #define REG_CLASS_NAMES \ {"NO_REGS", \ - "ACR_REGS", "MOF_REGS", "SRP_REGS", "CC0_REGS", \ + "MOF_REGS", "SRP_REGS", "CC0_REGS", \ "MOF_SRP_REGS", "SPECIAL_REGS", \ - "SPEC_ACR_REGS", "GENNONACR_REGS", "SPEC_GENNONACR_REGS", \ "GENERAL_REGS", "ALL_REGS"} #define CRIS_SPECIAL_REGS_CONTENTS \ @@ -472,37 +467,25 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ {0}, \ - {1 << CRIS_ACR_REGNUM}, \ {1 << CRIS_MOF_REGNUM}, \ {1 << CRIS_SRP_REGNUM}, \ {1 << CRIS_CC0_REGNUM}, \ {(1 << CRIS_MOF_REGNUM) \ | (1 << CRIS_SRP_REGNUM)}, \ {CRIS_SPECIAL_REGS_CONTENTS}, \ - {CRIS_SPECIAL_REGS_CONTENTS \ - | (1 << CRIS_ACR_REGNUM)}, \ - {(0xffff | CRIS_FAKED_REGS_CONTENTS) \ - & ~(1 << CRIS_ACR_REGNUM)}, \ - {(0xffff | CRIS_FAKED_REGS_CONTENTS \ - | CRIS_SPECIAL_REGS_CONTENTS) \ - & ~(1 << CRIS_ACR_REGNUM)}, \ {0xffff | CRIS_FAKED_REGS_CONTENTS}, \ {0xffff | CRIS_FAKED_REGS_CONTENTS \ | CRIS_SPECIAL_REGS_CONTENTS} \ } #define REGNO_REG_CLASS(REGNO) \ - ((REGNO) == CRIS_ACR_REGNUM ? ACR_REGS : \ - (REGNO) == CRIS_MOF_REGNUM ? MOF_REGS : \ + ((REGNO) == CRIS_MOF_REGNUM ? MOF_REGS : \ (REGNO) == CRIS_SRP_REGNUM ? SRP_REGS : \ (REGNO) == CRIS_CC0_REGNUM ? CC0_REGS : \ GENERAL_REGS) #define BASE_REG_CLASS GENERAL_REGS -#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OCODE, ICODE) \ - ((OCODE) != POST_INC ? BASE_REG_CLASS : GENNONACR_REGS) - #define INDEX_REG_CLASS GENERAL_REGS /* Since it uses reg_renumber, it is safe only once reg_renumber diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 9d1c179d5211..9d9eb8b7dbbf 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -60,7 +60,6 @@ (define_constants [(CRIS_STATIC_CHAIN_REGNUM 7) (CRIS_REAL_FP_REGNUM 8) (CRIS_SP_REGNUM 14) - (CRIS_ACR_REGNUM 15) (CRIS_SRP_REGNUM 16) (CRIS_MOF_REGNUM 17) (CRIS_AP_REGNUM 18)