Message ID | 20220124095029.8744-1-kito.cheng@sifive.com |
---|---|
State | New |
Headers | show |
Series | [committed] RISC-V: Fix testcase after bump isa spec version | expand |
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-19.c b/gcc/testsuite/gcc.target/riscv/attribute-19.c index 18f68d98561..562f8089361 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-19.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-19.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-mriscv-attribute -march=rv64imp0p9 -mabi=lp64" } */ +/* { dg-options "-mriscv-attribute -march=rv64imp0p9 -mabi=lp64 -misa-spec=2.2" } */ int foo() {} /* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_p0p9\"" } } */