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[7/7] arm: Add test for AES erratum mitigation

Message ID 20220120112724.830872-8-rearnsha@arm.com
State New
Headers show
Series Arm: mitigation for AES erratum on Cortex-a57 and Cortex-A72 | expand

Commit Message

Richard Earnshaw Jan. 20, 2022, 11:27 a.m. UTC 
Add a testcase for the erratum mitigation.  To improve coverage
use -dp on the assembler output and match the pattern names (and where
needed the alternative number).

gcc/testsuite/ChangeLog:

	* gcc.target/arm/crypto-vaese-erratum1.c: New test.
---
 .../gcc.target/arm/crypto-vaese-erratum1.c    | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vaese-erratum1.c
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Patch

diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaese-erratum1.c b/gcc/testsuite/gcc.target/arm/crypto-vaese-erratum1.c
new file mode 100644
index 00000000000..3f16688a8aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaese-erratum1.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-O2 -mfix-cortex-a57-aes-1742098 -dp" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+uint8x16_t
+foo (uint8x16_t v)
+{
+  const uint8x16_t key1 = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+			   0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
+  const uint8x16_t key2 = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+			   0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};
+  int i;
+
+  for (i = 0; i < 16; ++i)
+    {
+      v = vaesmcq_u8 (vaeseq_u8 (v, key1));
+      v = vaesmcq_u8 (vaeseq_u8 (v, key2));
+    }
+  return v;
+}
+
+/* { dg-final { scan-assembler "aese.8\tq\[0-9\]+, q\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "aes_op_protect/2" 2} } */
+/* { dg-final { scan-assembler-times "aes_op_protect/0" 1} } */
+/* { dg-final { scan-assembler-times "(?:aesmc|aese_fused)_protected" 1} } */