diff mbox series

[3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES

Message ID 20220120112724.830872-4-rearnsha@arm.com
State New
Headers show
Series Arm: mitigation for AES erratum on Cortex-a57 and Cortex-A72 | expand

Commit Message

Richard Earnshaw Jan. 20, 2022, 11:27 a.m. UTC 
Add a new option -mfix-cortex-a-aes for enabling the Cortex-A AES
erratum work-around and enable it automatically for the affected
products (Cortex-A57 and Cortex-A72).

gcc/ChangeLog:

	* config/arm/arm-cpus.in (quirk_aes_1742098): New quirk feature
	(ALL_QUIRKS): Add it.
	(cortex-a57, cortex-a72): Enable it.
	(cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise.
	* config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
	option.
	(mfix-cortex-a72-aes-1655431): New option alias.
	* config/arm/arm.cc (arm_option_override): Handle default settings
	for AES erratum switch.
	* doc/invoke.texi (Arm Options): Document new options.
---
 gcc/config/arm/arm-cpus.in |  9 ++++++++-
 gcc/config/arm/arm.cc      |  9 +++++++++
 gcc/config/arm/arm.opt     | 10 ++++++++++
 gcc/doc/invoke.texi        | 11 +++++++++++
 4 files changed, 38 insertions(+), 1 deletion(-)

Comments

Jakub Jelinek Jan. 27, 2022, 10:07 a.m. UTC | #1 
On Thu, Jan 20, 2022 at 11:27:20AM +0000, Richard Earnshaw via Gcc-patches wrote:
> gcc/ChangeLog:
> 
> 	* config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
> 	option.
> 	(mfix-cortex-a72-aes-1655431): New option alias.

> --- a/gcc/config/arm/arm.opt
> +++ b/gcc/config/arm/arm.opt
> @@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
>  Target Var(fix_vlldm) Init(2)
>  Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
>  
> +mfix-cortex-a57-aes-1742098
> +Target Var(fix_aes_erratum_1742098) Init(2) Save
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> +Arm erratum #1742098
> +
> +mfix-cortex-a72-aes-1655431
> +Target Alias(mfix-cortex-a57-aes-1742098)
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> +Arm erratum #1655431
> +
>  munaligned-access
>  Target Var(unaligned_access) Init(2) Save
>  Enable unaligned word and halfword accesses to packed data.

This breaks:
Running /usr/src/gcc/gcc/testsuite/gcc.misc-tests/help.exp ...
FAIL: compiler driver --help=target option(s): "^ +-.*[^:.]$" absent from output: "  -mfix-cortex-a57-aes-1742098 Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72. Arm erratum #1742098"

help.exp with help of lib/options.exp tests whether all non-empty descriptions of
options are terminated with . or :.

The following patch fixes that, ok for trunk?

2022-01-27  Jakub Jelinek  <jakub@redhat.com>

	* config/arm/arm.opt (mfix-cortex-a57-aes-1742098,
	mfix-cortex-a72-aes-1655431): Ensure description ends with full stop.

--- gcc/config/arm/arm.opt.jj	2022-01-21 22:43:22.879719389 +0100
+++ gcc/config/arm/arm.opt	2022-01-27 11:02:29.457553296 +0100
@@ -274,13 +274,13 @@ Mitigate issues with VLLDM on some M-pro
 
 mfix-cortex-a57-aes-1742098
 Target Var(fix_aes_erratum_1742098) Init(2) Save
-Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
-Arm erratum #1742098
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
+(Arm erratum #1742098).
 
 mfix-cortex-a72-aes-1655431
 Target Alias(mfix-cortex-a57-aes-1742098)
-Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
-Arm erratum #1655431
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
+(Arm erratum #1655431).
 
 munaligned-access
 Target Var(unaligned_access) Init(2) Save

	Jakub
Jakub Jelinek Feb. 3, 2022, 1:20 p.m. UTC | #2 
Hi!

I'd like to ping the following patch.

Thanks.

On Thu, Jan 27, 2022 at 11:07:26AM +0100, Jakub Jelinek via Gcc-patches wrote:
> On Thu, Jan 20, 2022 at 11:27:20AM +0000, Richard Earnshaw via Gcc-patches wrote:
> > gcc/ChangeLog:
> > 
> > 	* config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
> > 	option.
> > 	(mfix-cortex-a72-aes-1655431): New option alias.
> 
> > --- a/gcc/config/arm/arm.opt
> > +++ b/gcc/config/arm/arm.opt
> > @@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
> >  Target Var(fix_vlldm) Init(2)
> >  Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
> >  
> > +mfix-cortex-a57-aes-1742098
> > +Target Var(fix_aes_erratum_1742098) Init(2) Save
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > +Arm erratum #1742098
> > +
> > +mfix-cortex-a72-aes-1655431
> > +Target Alias(mfix-cortex-a57-aes-1742098)
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > +Arm erratum #1655431
> > +
> >  munaligned-access
> >  Target Var(unaligned_access) Init(2) Save
> >  Enable unaligned word and halfword accesses to packed data.
> 
> This breaks:
> Running /usr/src/gcc/gcc/testsuite/gcc.misc-tests/help.exp ...
> FAIL: compiler driver --help=target option(s): "^ +-.*[^:.]$" absent from output: "  -mfix-cortex-a57-aes-1742098 Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72. Arm erratum #1742098"
> 
> help.exp with help of lib/options.exp tests whether all non-empty descriptions of
> options are terminated with . or :.
> 
> The following patch fixes that, ok for trunk?
> 
> 2022-01-27  Jakub Jelinek  <jakub@redhat.com>
> 
> 	* config/arm/arm.opt (mfix-cortex-a57-aes-1742098,
> 	mfix-cortex-a72-aes-1655431): Ensure description ends with full stop.
> 
> --- gcc/config/arm/arm.opt.jj	2022-01-21 22:43:22.879719389 +0100
> +++ gcc/config/arm/arm.opt	2022-01-27 11:02:29.457553296 +0100
> @@ -274,13 +274,13 @@ Mitigate issues with VLLDM on some M-pro
>  
>  mfix-cortex-a57-aes-1742098
>  Target Var(fix_aes_erratum_1742098) Init(2) Save
> -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> -Arm erratum #1742098
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> +(Arm erratum #1742098).
>  
>  mfix-cortex-a72-aes-1655431
>  Target Alias(mfix-cortex-a57-aes-1742098)
> -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> -Arm erratum #1655431
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> +(Arm erratum #1655431).
>  
>  munaligned-access
>  Target Var(unaligned_access) Init(2) Save

	Jakub
Richard Biener Feb. 3, 2022, 1:28 p.m. UTC | #3 
On Thu, Feb 3, 2022 at 2:21 PM Jakub Jelinek via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi!
>
> I'd like to ping the following patch.

OK (note the patch is obvious IMHO)

Richard.

> Thanks.
>
> On Thu, Jan 27, 2022 at 11:07:26AM +0100, Jakub Jelinek via Gcc-patches wrote:
> > On Thu, Jan 20, 2022 at 11:27:20AM +0000, Richard Earnshaw via Gcc-patches wrote:
> > > gcc/ChangeLog:
> > >
> > >     * config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
> > >     option.
> > >     (mfix-cortex-a72-aes-1655431): New option alias.
> >
> > > --- a/gcc/config/arm/arm.opt
> > > +++ b/gcc/config/arm/arm.opt
> > > @@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
> > >  Target Var(fix_vlldm) Init(2)
> > >  Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
> > >
> > > +mfix-cortex-a57-aes-1742098
> > > +Target Var(fix_aes_erratum_1742098) Init(2) Save
> > > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > > +Arm erratum #1742098
> > > +
> > > +mfix-cortex-a72-aes-1655431
> > > +Target Alias(mfix-cortex-a57-aes-1742098)
> > > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > > +Arm erratum #1655431
> > > +
> > >  munaligned-access
> > >  Target Var(unaligned_access) Init(2) Save
> > >  Enable unaligned word and halfword accesses to packed data.
> >
> > This breaks:
> > Running /usr/src/gcc/gcc/testsuite/gcc.misc-tests/help.exp ...
> > FAIL: compiler driver --help=target option(s): "^ +-.*[^:.]$" absent from output: "  -mfix-cortex-a57-aes-1742098 Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72. Arm erratum #1742098"
> >
> > help.exp with help of lib/options.exp tests whether all non-empty descriptions of
> > options are terminated with . or :.
> >
> > The following patch fixes that, ok for trunk?
> >
> > 2022-01-27  Jakub Jelinek  <jakub@redhat.com>
> >
> >       * config/arm/arm.opt (mfix-cortex-a57-aes-1742098,
> >       mfix-cortex-a72-aes-1655431): Ensure description ends with full stop.
> >
> > --- gcc/config/arm/arm.opt.jj 2022-01-21 22:43:22.879719389 +0100
> > +++ gcc/config/arm/arm.opt    2022-01-27 11:02:29.457553296 +0100
> > @@ -274,13 +274,13 @@ Mitigate issues with VLLDM on some M-pro
> >
> >  mfix-cortex-a57-aes-1742098
> >  Target Var(fix_aes_erratum_1742098) Init(2) Save
> > -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > -Arm erratum #1742098
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> > +(Arm erratum #1742098).
> >
> >  mfix-cortex-a72-aes-1655431
> >  Target Alias(mfix-cortex-a57-aes-1742098)
> > -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > -Arm erratum #1655431
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> > +(Arm erratum #1655431).
> >
> >  munaligned-access
> >  Target Var(unaligned_access) Init(2) Save
>
>         Jakub
>
diff mbox series

Patch

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 499e82d790d..0d3082b569f 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -192,6 +192,9 @@  define feature quirk_cm3_ldrd
 # v8-m/v8.1-m VLLDM errata.
 define feature quirk_vlldm
 
+# AES errata on some Cortex-A parts
+define feature quirk_aes_1742098
+
 # Don't use .cpu assembly directive
 define feature quirk_no_asmcpu
 
@@ -329,7 +332,7 @@  define implied vfp_base MVE MVE_FP ALL_FP
 # architectures.
 # xscale isn't really a 'quirk', but it isn't an architecture either and we
 # need to ignore it for matching purposes.
-define fgroup ALL_QUIRKS   quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu
+define fgroup ALL_QUIRKS   quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu quirk_aes_1742098
 
 define fgroup IGNORE_FOR_MULTILIB cdecp0 cdecp1 cdecp2 cdecp3 cdecp4 cdecp5 cdecp6 cdecp7
 
@@ -1342,6 +1345,7 @@  begin cpu cortex-a57
  cname cortexa57
  tune flags LDSCHED
  architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
  vendor 41
@@ -1353,6 +1357,7 @@  begin cpu cortex-a72
  tune for cortex-a57
  tune flags LDSCHED
  architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
  vendor 41
@@ -1391,6 +1396,7 @@  begin cpu cortex-a57.cortex-a53
  tune for cortex-a53
  tune flags LDSCHED
  architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
 end cpu cortex-a57.cortex-a53
@@ -1400,6 +1406,7 @@  begin cpu cortex-a72.cortex-a53
  tune for cortex-a53
  tune flags LDSCHED
  architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
  option crypto add FP_ARMv8 CRYPTO
  costs cortex_a57
 end cpu cortex-a72.cortex-a53
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 7825e364c01..04354b36606 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3638,6 +3638,15 @@  arm_option_override (void)
 	fix_vlldm = 0;
     }
 
+  /* Enable fix_aes by default if required.  */
+  if (fix_aes_erratum_1742098 == 2)
+    {
+      if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_aes_1742098))
+	fix_aes_erratum_1742098 = 1;
+      else
+	fix_aes_erratum_1742098 = 0;
+    }
+
   /* Hot/Cold partitioning is not currently supported, since we can't
      handle literal pool placement in that case.  */
   if (flag_reorder_blocks_and_partition)
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index 587fc932f96..2a4f165033a 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -272,6 +272,16 @@  mfix-cmse-cve-2021-35465
 Target Var(fix_vlldm) Init(2)
 Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
 
+mfix-cortex-a57-aes-1742098
+Target Var(fix_aes_erratum_1742098) Init(2) Save
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
+Arm erratum #1742098
+
+mfix-cortex-a72-aes-1655431
+Target Alias(mfix-cortex-a57-aes-1742098)
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
+Arm erratum #1655431
+
 munaligned-access
 Target Var(unaligned_access) Init(2) Save
 Enable unaligned word and halfword accesses to packed data.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 58751c48b8e..67693d6c5cf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -812,6 +812,8 @@  Objective-C and Objective-C++ Dialects}.
 -mtp=@var{name}  -mtls-dialect=@var{dialect} @gol
 -mword-relocations @gol
 -mfix-cortex-m3-ldrd @gol
+-mfix-cortex-a57-aes-1742098 @gol
+-mfix-cortex-a72-aes-1655431 @gol
 -munaligned-access @gol
 -mneon-for-64bits @gol
 -mslow-flash-data @gol
@@ -21281,6 +21283,15 @@  with overlapping destination and base registers are used.  This option avoids
 generating these instructions.  This option is enabled by default when
 @option{-mcpu=cortex-m3} is specified.
 
+@item -mfix-cortex-a57-aes-1742098
+@itemx -mno-fix-cortex-a57-aes-1742098
+@itemx -mfix-cortex-a72-aes-1655431
+@itemx -mno-fix-cortex-a72-aes-1655431
+Enable (disable) mitigation for an erratum on Cortex-A57 and
+Cortex-A72 that affects the AES cryptographic instructions.  This
+option is enabled by default when either @option{-mcpu=cortex-a57} or
+@option{-mcpu=cortex-a72} is specified.
+
 @item -munaligned-access
 @itemx -mno-unaligned-access
 @opindex munaligned-access