Message ID | 20211028065501.5373-1-kito.cheng@sifive.com |
---|---|
State | New |
Headers | show |
Series | [committed] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern | expand |
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index dd4c24292f2..225e5b259c1 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1311,7 +1311,7 @@ (define_insn_and_split "*zero_extendsidi2_internal" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)" + "TARGET_64BIT && !TARGET_ZBA" "@ # lwu\t%0,%1"